Map TRACE Report

Loading design for application trce from file counter_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LFXP2-5E
Package:     TQFP144
Performance: 5
Loading device for application trce from file 'mg5a26x29.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 11.5.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Fri Apr 29 17:40:22 2022

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -c -u 0 -gt -mapchkpnt 0 -sethld -o Counter_impl1.tw1 -gui -msgset C:/Users/Dayalan Nair/Desktop/UCT-FPGA-Course-2022/dnair_practicals/Counter/promote.xml Counter_impl1_map.ncd Counter_impl1.prf 
Design file:     counter_impl1_map.ncd
Preference file: counter_impl1.prf
Device,speed:    LFXP2-5E,5
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

Preference Summary


  • FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
    •             4096 items scored, 0 timing errors detected.
Report:  105.831MHz is the maximum frequency for this preference.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • Unconstrained: CLOCK_DOMAIN
    •             2608 unconstrained paths found


  • Unconstrained: INPUT_SETUP
    •             0 unconstrained paths found


  • Unconstrained: CLOCK_TO_OUT
    •             1 unconstrained path found


  • Unconstrained: MAXDELAY
    •             0 unconstrained paths found

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 10.551ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              UART_Inst/clk_cnt[2]  (from ipClk_c +)
   Destination:    FF         Data in        UART_Inst/tx_cnt[3]  (to ipClk_c +)

   Delay:               9.005ns  (28.0% logic, 72.0% route), 7 logic levels.

 Constraint Details:

      9.005ns physical path delay UART_Inst/SLICE_17 to UART_Inst/SLICE_89 meets
     20.000ns delay constraint less
      0.444ns LSR_SET requirement (totaling 19.556ns) by 10.551ns

 Physical Path Details:

      Data path UART_Inst/SLICE_17 to UART_Inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_17.CLK to *t/SLICE_17.Q1 UART_Inst/SLICE_17 (from ipClk_c)
ROUTE         3   e 1.081 *t/SLICE_17.Q1 to */SLICE_451.D0 reveal_ist_31
CTOF_DEL    ---     0.260 */SLICE_451.D0 to */SLICE_451.F0 UART_Inst/SLICE_451
ROUTE         1   e 1.081 */SLICE_451.F0 to */SLICE_352.A1 UART_Inst/un1_tx_state_3_0_o2_5
CTOF_DEL    ---     0.260 */SLICE_352.A1 to */SLICE_352.F1 UART_Inst/SLICE_352
ROUTE         8   e 1.081 */SLICE_352.F1 to *t/SLICE_90.A1 UART_Inst/un1_tx_state_3_0_o2
CTOF_DEL    ---     0.260 *t/SLICE_90.A1 to *t/SLICE_90.F1 UART_Inst/SLICE_90
ROUTE         4   e 1.081 *t/SLICE_90.F1 to */SLICE_455.A1 UART_Inst/N_61
CTOF_DEL    ---     0.260 */SLICE_455.A1 to */SLICE_455.F1 UART_Inst/SLICE_455
ROUTE         4   e 1.081 */SLICE_455.F1 to *st/SLICE_5.B0 UART_Inst/N_99
C0TOFCO_DE  ---     0.790 *st/SLICE_5.B0 to *t/SLICE_5.FCO UART_Inst/SLICE_5
ROUTE         1   e 0.001 *t/SLICE_5.FCO to *t/SLICE_4.FCI UART_Inst/un1_tx_cnt_7_cry_2
FCITOF0_DE  ---     0.305 *t/SLICE_4.FCI to *st/SLICE_4.F0 UART_Inst/SLICE_4
ROUTE         1   e 1.081 *st/SLICE_4.F0 to */SLICE_89.LSR UART_Inst/un1_tx_cnt_7_s_3_0_S0 (to ipClk_c)
                  --------
                    9.005   (28.0% logic, 72.0% route), 7 logic levels.

Report:  105.831MHz is the maximum frequency for this preference.


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipnReset
   Destination:    FF         Data in        UART_Inst/rst  (to ipClk_c +)

   Delay:               2.200ns  (50.8% logic, 49.2% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.858         19.PAD to       19.PADDI ipnReset
ROUTE         1   e 1.081       19.PADDI to *t/SLICE_52.A0 ipnReset_c
CTOF_DEL    ---     0.260 *t/SLICE_52.A0 to *t/SLICE_52.F0 UART_Inst/SLICE_52
ROUTE         1   e 0.001 *t/SLICE_52.F0 to */SLICE_52.DI0 UART_Inst/ipnReset_c_i (to ipClk_c)
                  --------
                    2.200   (50.8% logic, 49.2% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        UART_Inst_rxio  (to ipClk_c +)

   Delay:               1.939ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.858        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 1.081      110.PADDI to *T_Rx_MGIOL.DI ipUART_Rx_c (to ipClk_c)
                  --------
                    1.939   (44.2% logic, 55.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]  (to ipClk_c +)

   Delay:               1.939ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.858        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 1.081      110.PADDI to */SLICE_216.M0 ipUART_Rx_c (to ipClk_c)
                  --------
                    1.939   (44.2% logic, 55.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]  (to ipClk_c +)

   Delay:               1.939ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.858        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 1.081      110.PADDI to */SLICE_238.M1 ipUART_Rx_c (to ipClk_c)
                  --------
                    1.939   (44.2% logic, 55.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: Unconstrained: CLOCK_DOMAIN
            2608 unconstrained paths found
--------------------------------------------------------------------------------

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    9.297ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (9.204ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_372.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_372.A1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    9.204   (26.5% logic, 73.5% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    9.297ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (9.204ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_274.CLK to */SLICE_274.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_274.Q0 to */SLICE_372.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]
CTOF_DEL    ---     0.260 */SLICE_372.C1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    9.204   (26.5% logic, 73.5% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_122.CLK to */SLICE_122.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c)
ROUTE         4   e 1.081 */SLICE_122.Q1 to */SLICE_459.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.260 */SLICE_459.B1 to */SLICE_459.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         1   e 1.081 */SLICE_459.F1 to */SLICE_345.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.260 */SLICE_345.D0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_345.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_345.A0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_345.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_345.A0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_122.CLK to */SLICE_122.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c)
ROUTE         5   e 1.081 */SLICE_122.Q0 to */SLICE_459.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.260 */SLICE_459.A1 to */SLICE_459.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         1   e 1.081 */SLICE_459.F1 to */SLICE_345.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.260 */SLICE_345.D0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_459.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_459.C1 to */SLICE_459.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         1   e 1.081 */SLICE_459.F1 to */SLICE_345.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.260 */SLICE_345.D0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (8.709ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_345.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_345.A0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    8.709   (22.3% logic, 77.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_371 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_371.CLK to */SLICE_371.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_371 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_371.Q0 to */SLICE_372.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]
CTOF_DEL    ---     0.260 */SLICE_372.C0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_372.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_372.B0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.757ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.664ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.664   (25.1% logic, 74.9% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.523ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.430ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_447.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_447.A0 to */SLICE_447.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_447
ROUTE         1   e 1.081 */SLICE_447.F0 to */SLICE_400.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_m_N_4L5_0_sx
CTOF_DEL    ---     0.260 */SLICE_400.C1 to */SLICE_400.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         7   e 1.081 */SLICE_400.F1 to */SLICE_375.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_RNI03VU1[4]
CTOF_DEL    ---     0.260 */SLICE_375.D1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.430   (23.0% logic, 77.0% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.523ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.430ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_447.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_447.D0 to */SLICE_447.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_447
ROUTE         1   e 1.081 */SLICE_447.F0 to */SLICE_400.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_m_N_4L5_0_sx
CTOF_DEL    ---     0.260 */SLICE_400.C1 to */SLICE_400.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         7   e 1.081 */SLICE_400.F1 to */SLICE_375.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_RNI03VU1[4]
CTOF_DEL    ---     0.260 */SLICE_375.D1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.430   (23.0% logic, 77.0% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.496ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (8.403ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_372.CLK to */SLICE_372.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372 (from ipClk_c)
ROUTE         2   e 0.280 */SLICE_372.Q0 to */SLICE_372.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]
CTOF_DEL    ---     0.260 */SLICE_372.B1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.403   (29.0% logic, 71.0% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.956ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.863ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_366.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_366.A0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.863   (27.7% logic, 72.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.956ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.863ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_310.CLK to */SLICE_310.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_310.Q0 to */SLICE_366.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]
CTOF_DEL    ---     0.260 */SLICE_366.C0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.863   (27.7% logic, 72.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_33.Q0 to */SLICE_400.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_400.B0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_375.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_375.A0 to */SLICE_375.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 0.280 */SLICE_375.F0 to */SLICE_375.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_28
CTOF_DEL    ---     0.260 */SLICE_375.A1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_372.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_372.A1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_33.Q1 to */SLICE_400.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_400.C0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_375.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_375.A0 to */SLICE_375.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 0.280 */SLICE_375.F0 to */SLICE_375.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_28
CTOF_DEL    ---     0.260 */SLICE_375.A1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_34.Q1 to */SLICE_400.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_400.A0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_375.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_375.A0 to */SLICE_375.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 0.280 */SLICE_375.F0 to */SLICE_375.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_28
CTOF_DEL    ---     0.260 */SLICE_375.A1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_32.Q0 to */SLICE_400.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_400.D0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_375.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_375.A0 to */SLICE_375.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 0.280 */SLICE_375.F0 to */SLICE_375.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_28
CTOF_DEL    ---     0.260 */SLICE_375.A1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.722ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.629ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_274.CLK to */SLICE_274.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_274.Q0 to */SLICE_372.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]
CTOF_DEL    ---     0.260 */SLICE_372.C1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.629   (25.5% logic, 74.5% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.650ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_280 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.557ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_280.CLK to */SLICE_280.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_280 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_280.Q0 to */SLICE_327.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.A0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.557   (28.5% logic, 71.5% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.650ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_283 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.557ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_283.CLK to */SLICE_283.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_283 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_283.Q0 to */SLICE_327.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.D1 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.557   (28.5% logic, 71.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.650ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.557ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_327.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOOFX_DEL  ---     0.494 */SLICE_327.B0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.557   (28.5% logic, 71.5% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.650ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_281 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.557ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_281.CLK to */SLICE_281.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_281 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_281.Q0 to */SLICE_327.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.C0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.557   (28.5% logic, 71.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_454.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_454.B1 to */SLICE_454.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_454
ROUTE         2   e 1.081 */SLICE_454.F1 to */SLICE_361.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5
CTOF_DEL    ---     0.260 */SLICE_361.A0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_441.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_441.B0 to */SLICE_441.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_441
ROUTE         1   e 1.081 */SLICE_441.F0 to */SLICE_361.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.wen_te11_2
CTOF_DEL    ---     0.260 */SLICE_361.B0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_363.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_363.A0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_361.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_361.C0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_454.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_454.A1 to */SLICE_454.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_454
ROUTE         2   e 1.081 */SLICE_454.F1 to */SLICE_361.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5
CTOF_DEL    ---     0.260 */SLICE_361.A0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_441.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_441.A0 to */SLICE_441.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_441
ROUTE         1   e 1.081 */SLICE_441.F0 to */SLICE_361.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.wen_te11_2
CTOF_DEL    ---     0.260 */SLICE_361.B0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_363.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_363.B0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_361.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_361.C0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_454.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_454.C1 to */SLICE_454.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_454
ROUTE         2   e 1.081 */SLICE_454.F1 to */SLICE_361.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5
CTOF_DEL    ---     0.260 */SLICE_361.A0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_441.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_441.C0 to */SLICE_441.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_441
ROUTE         1   e 1.081 */SLICE_441.F0 to */SLICE_361.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.wen_te11_2
CTOF_DEL    ---     0.260 */SLICE_361.B0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        16   e 1.081 *u/SLICE_95.Q1 to */SLICE_441.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[3]
CTOF_DEL    ---     0.260 */SLICE_441.D0 to */SLICE_441.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_441
ROUTE         1   e 1.081 */SLICE_441.F0 to */SLICE_361.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.wen_te11_2
CTOF_DEL    ---     0.260 */SLICE_361.B0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_345.B0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_345.B0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (7.368ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_454.D1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_454.D1 to */SLICE_454.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_454
ROUTE         2   e 1.081 */SLICE_454.F1 to */SLICE_361.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5
CTOF_DEL    ---     0.260 */SLICE_361.A0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    7.368   (22.8% logic, 77.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_363.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_363.B0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_374.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_374.C0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_31.CLK to *u/SLICE_31.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *u/SLICE_31.Q0 to */SLICE_401.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_401.B0 to */SLICE_401.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_401
ROUTE         3   e 1.081 */SLICE_401.F0 to */SLICE_329.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_11_1
CTOOFX_DEL  ---     0.494 */SLICE_329.D0 to *LICE_329.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_RNIRJH44/SLICE_329
ROUTE         2   e 1.081 *LICE_329.OFX0 to */SLICE_415.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_1
CTOF_DEL    ---     0.260 */SLICE_415.C0 to */SLICE_415.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_415
ROUTE         1   e 1.081 */SLICE_415.F0 to */SLICE_406.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_13
CTOF_DEL    ---     0.260 */SLICE_406.D1 to */SLICE_406.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         1   e 1.081 */SLICE_406.F1 to */SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
CTOF_DEL    ---     0.260 */SLICE_123.D0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *u/SLICE_32.Q1 to */SLICE_401.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_401.A0 to */SLICE_401.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_401
ROUTE         3   e 1.081 */SLICE_401.F0 to */SLICE_329.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_11_1
CTOOFX_DEL  ---     0.494 */SLICE_329.D0 to *LICE_329.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_RNIRJH44/SLICE_329
ROUTE         2   e 1.081 *LICE_329.OFX0 to */SLICE_415.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_1
CTOF_DEL    ---     0.260 */SLICE_415.C0 to */SLICE_415.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_415
ROUTE         1   e 1.081 */SLICE_415.F0 to */SLICE_406.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_13
CTOF_DEL    ---     0.260 */SLICE_406.D1 to */SLICE_406.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         1   e 1.081 */SLICE_406.F1 to */SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
CTOF_DEL    ---     0.260 */SLICE_123.D0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_349.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_349.D0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_363.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_363.A0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_374.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_374.C0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.416ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.323ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_247.CLK to */SLICE_247.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_247.Q0 to */SLICE_447.D1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.260 */SLICE_447.D1 to */SLICE_447.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_447
ROUTE         1   e 1.081 */SLICE_447.F1 to */SLICE_329.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_3_sx_sx
CTOOFX_DEL  ---     0.494 */SLICE_329.D1 to *LICE_329.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_RNIRJH44/SLICE_329
ROUTE         2   e 1.081 *LICE_329.OFX0 to */SLICE_415.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_1
CTOF_DEL    ---     0.260 */SLICE_415.C0 to */SLICE_415.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_415
ROUTE         1   e 1.081 */SLICE_415.F0 to */SLICE_406.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_13
CTOF_DEL    ---     0.260 */SLICE_406.D1 to */SLICE_406.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         1   e 1.081 */SLICE_406.F1 to */SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
CTOF_DEL    ---     0.260 */SLICE_123.D0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.323   (26.2% logic, 73.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_123.CLK to */SLICE_123.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_123.Q0 to */SLICE_546.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc
CTOF_DEL    ---     0.260 */SLICE_546.B0 to */SLICE_546.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 1.081 */SLICE_546.F0 to */SLICE_406.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_0
CTOF_DEL    ---     0.260 */SLICE_406.A0 to */SLICE_406.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         2   e 1.081 */SLICE_406.F0 to */SLICE_414.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_1_0
CTOF_DEL    ---     0.260 */SLICE_414.B0 to */SLICE_414.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_414
ROUTE         1   e 1.081 */SLICE_414.F0 to */SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5
CTOF_DEL    ---     0.260 */SLICE_411.B1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_489.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_489.B0 to */SLICE_489.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_489
ROUTE         1   e 1.081 */SLICE_489.F0 to */SLICE_363.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[1]
CTOF_DEL    ---     0.260 */SLICE_363.A1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_364.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_364.B0 to */SLICE_364.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         4   e 1.081 */SLICE_364.F0 to */SLICE_363.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_tu
CTOF_DEL    ---     0.260 */SLICE_363.D1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_364.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_364.A0 to */SLICE_364.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         4   e 1.081 */SLICE_364.F0 to */SLICE_363.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_tu
CTOF_DEL    ---     0.260 */SLICE_363.D1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_371 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_371.CLK to */SLICE_371.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_371 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_371.Q0 to */SLICE_372.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]
CTOF_DEL    ---     0.260 */SLICE_372.C0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_310.CLK to */SLICE_310.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_310.Q1 to */SLICE_478.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]
CTOF_DEL    ---     0.260 */SLICE_478.B0 to */SLICE_478.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_478
ROUTE         1   e 1.081 */SLICE_478.F0 to */SLICE_363.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][1]
CTOF_DEL    ---     0.260 */SLICE_363.B1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_372.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_372.B0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_478.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_478.A0 to */SLICE_478.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_478
ROUTE         1   e 1.081 */SLICE_478.F0 to */SLICE_363.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][1]
CTOF_DEL    ---     0.260 */SLICE_363.B1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_489.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_489.A0 to */SLICE_489.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_489
ROUTE         1   e 1.081 */SLICE_489.F0 to */SLICE_363.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[1]
CTOF_DEL    ---     0.260 */SLICE_363.A1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_546.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_546.A0 to */SLICE_546.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 1.081 */SLICE_546.F0 to */SLICE_406.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_0
CTOF_DEL    ---     0.260 */SLICE_406.A0 to */SLICE_406.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         2   e 1.081 */SLICE_406.F0 to */SLICE_414.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_1_0
CTOF_DEL    ---     0.260 */SLICE_414.B0 to */SLICE_414.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_414
ROUTE         1   e 1.081 */SLICE_414.F0 to */SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5
CTOF_DEL    ---     0.260 */SLICE_411.B1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.182ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (7.089ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_274.CLK to */SLICE_274.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_274 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_274.Q1 to */SLICE_489.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]
CTOF_DEL    ---     0.260 */SLICE_489.C0 to */SLICE_489.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_489
ROUTE         1   e 1.081 */SLICE_489.F0 to */SLICE_363.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[1]
CTOF_DEL    ---     0.260 */SLICE_363.A1 to */SLICE_363.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         1   e 1.081 */SLICE_363.F1 to */SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.260 */SLICE_394.A0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    7.089   (23.7% logic, 76.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.155ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (7.062ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_366.CLK to */SLICE_366.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366 (from ipClk_c)
ROUTE         5   e 0.280 */SLICE_366.Q0 to */SLICE_366.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]
CTOF_DEL    ---     0.260 */SLICE_366.B0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_404.C1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.062   (30.8% logic, 69.2% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.072ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.828ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.828   (20.8% logic, 79.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.921ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.828ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_372.CLK to */SLICE_372.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372 (from ipClk_c)
ROUTE         2   e 0.280 */SLICE_372.Q0 to */SLICE_372.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]
CTOF_DEL    ---     0.260 */SLICE_372.B1 to */SLICE_372.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 0.280 */SLICE_372.F1 to */SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.260 */SLICE_372.A0 to */SLICE_372.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_372
ROUTE         1   e 1.081 */SLICE_372.F0 to */SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.260 */SLICE_366.C1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.828   (28.5% logic, 71.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.811ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.567ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 0.280 */SLICE_345.Q0 to */SLICE_345.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_345.C0 to */SLICE_345.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345
ROUTE         5   e 1.081 */SLICE_345.F0 to */SLICE_361.D0 top_reveal_coretop_instance/top_la0_inst_0/wen
CTOF_DEL    ---     0.260 */SLICE_361.D0 to */SLICE_361.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361
ROUTE         2   e 1.081 */SLICE_361.F0 to */SLICE_370.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.260 */SLICE_370.D1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.567   (25.6% logic, 74.4% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.615ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (6.522ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_185.CLK to */SLICE_185.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_185.Q0 to */SLICE_349.B1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
CTOF_DEL    ---     0.260 */SLICE_349.B1 to */SLICE_349.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 0.280 */SLICE_349.F1 to */SLICE_349.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_36
CTOF_DEL    ---     0.260 */SLICE_349.A0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.522   (29.4% logic, 70.6% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.615ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (6.522ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_174.CLK to */SLICE_174.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_174.Q0 to */SLICE_349.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.260 */SLICE_349.C1 to */SLICE_349.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 0.280 */SLICE_349.F1 to */SLICE_349.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_36
CTOF_DEL    ---     0.260 */SLICE_349.A0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.522   (29.4% logic, 70.6% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_549.CLK to */SLICE_549.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 (from ipClk_c)
ROUTE         5   e 1.081 */SLICE_549.Q0 to */SLICE_487.C0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
CTOF_DEL    ---     0.260 */SLICE_487.C0 to */SLICE_487.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487
ROUTE         1   e 1.081 */SLICE_487.F0 to */SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.260 */SLICE_364.A1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_487.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_487.A0 to */SLICE_487.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487
ROUTE         1   e 1.081 */SLICE_487.F0 to */SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.260 */SLICE_364.A1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_405.CLK to */SLICE_405.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_405.Q0 to */SLICE_456.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.260 */SLICE_456.C1 to */SLICE_456.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456
ROUTE         1   e 1.081 */SLICE_456.F1 to */SLICE_403.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_115_0
CTOF_DEL    ---     0.260 */SLICE_403.B1 to */SLICE_403.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_403
ROUTE         1   e 1.081 */SLICE_403.F1 to */SLICE_409.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1_1
CTOF_DEL    ---     0.260 */SLICE_409.B1 to */SLICE_409.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_409
ROUTE         1   e 1.081 */SLICE_409.F1 to */SLICE_123.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1
CTOF_DEL    ---     0.260 */SLICE_123.B1 to */SLICE_123.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.280 */SLICE_123.F1 to */SLICE_123.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_1
CTOF_DEL    ---     0.260 */SLICE_123.B0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_405.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_405.A1 to */SLICE_405.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405
ROUTE         1   e 0.280 */SLICE_405.F1 to */SLICE_405.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_1
CTOF_DEL    ---     0.260 */SLICE_405.A0 to */SLICE_405.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405
ROUTE         1   e 1.081 */SLICE_405.F0 to */SLICE_376.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/rd_dout_tm_m_1[0]
CTOF_DEL    ---     0.260 */SLICE_376.C1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_136.CLK to */SLICE_136.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_136.Q1 to */SLICE_458.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.260 */SLICE_458.B0 to */SLICE_458.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_458
ROUTE         1   e 1.081 */SLICE_458.F0 to */SLICE_376.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1
CTOF_DEL    ---     0.260 */SLICE_376.B0 to */SLICE_376.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 0.280 */SLICE_376.F0 to */SLICE_376.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1_RNI0K811
CTOF_DEL    ---     0.260 */SLICE_376.B1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_479.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_479.A0 to */SLICE_479.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_479
ROUTE         1   e 1.081 */SLICE_479.F0 to */SLICE_364.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][2]
CTOF_DEL    ---     0.260 */SLICE_364.B1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_136.CLK to */SLICE_136.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_136.Q0 to */SLICE_458.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]
CTOF_DEL    ---     0.260 */SLICE_458.A0 to */SLICE_458.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_458
ROUTE         1   e 1.081 */SLICE_458.F0 to */SLICE_376.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1
CTOF_DEL    ---     0.260 */SLICE_376.B0 to */SLICE_376.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 0.280 */SLICE_376.F0 to */SLICE_376.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1_RNI0K811
CTOF_DEL    ---     0.260 */SLICE_376.B1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_310.CLK to */SLICE_310.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_310 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_310.Q0 to */SLICE_366.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]
CTOF_DEL    ---     0.260 */SLICE_366.C0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_363.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_363.A0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_364.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_364.C1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_363.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_363.B0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_364.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_364.C1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_487.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_487.B0 to */SLICE_487.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487
ROUTE         1   e 1.081 */SLICE_487.F0 to */SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.260 */SLICE_364.A1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_366.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_366.A0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_174.CLK to */SLICE_174.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_174.Q0 to */SLICE_458.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.260 */SLICE_458.C0 to */SLICE_458.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_458
ROUTE         1   e 1.081 */SLICE_458.F0 to */SLICE_376.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1
CTOF_DEL    ---     0.260 */SLICE_376.B0 to */SLICE_376.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 0.280 */SLICE_376.F0 to */SLICE_376.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1_RNI0K811
CTOF_DEL    ---     0.260 */SLICE_376.B1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.381ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (6.288ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 0.280 */SLICE_408.Q0 to */SLICE_408.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_408.D1 to */SLICE_408.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408
ROUTE         7   e 1.081 */SLICE_408.F1 to */SLICE_375.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_1_1
CTOF_DEL    ---     0.260 */SLICE_375.B1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.288   (26.8% logic, 73.2% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_544.A0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_544.A0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_544.A0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_544.A0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_544.A0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_544.A0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_397.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_397.A0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_544.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_544.B0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_544.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_544.B0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_544.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_544.B0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.271ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (6.027ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    6.027   (23.6% logic, 76.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_398.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_398.A0 to */SLICE_398.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_398
ROUTE         9   e 1.081 */SLICE_398.F0 to */SLICE_347.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un3_jtdo
CTOF_DEL    ---     0.260 */SLICE_347.C0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_31.CLK to *u/SLICE_31.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *u/SLICE_31.Q0 to */SLICE_401.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_401.B0 to */SLICE_401.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_401
ROUTE         3   e 1.081 */SLICE_401.F0 to */SLICE_347.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_11_1
CTOF_DEL    ---     0.260 */SLICE_347.A0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_281 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_281.CLK to */SLICE_281.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_281 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_281.Q0 to */SLICE_327.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.C0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_162.CLK to */SLICE_162.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_162.Q0 to */SLICE_349.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.260 */SLICE_349.C0 to */SLICE_349.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_349
ROUTE         1   e 1.081 */SLICE_349.F0 to */SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
CTOF_DEL    ---     0.260 */SLICE_404.A1 to */SLICE_404.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_404
ROUTE         1   e 1.081 */SLICE_404.F1 to */SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
CTOOFX_DEL  ---     0.494 */SLICE_328.D1 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_458.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_458.A1 to */SLICE_458.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_458
ROUTE         1   e 1.081 */SLICE_458.F1 to */SLICE_374.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un3_jtdo_first_bit
CTOF_DEL    ---     0.260 */SLICE_374.D1 to */SLICE_374.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         1   e 1.081 */SLICE_374.F1 to */SLICE_328.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_25
CTOOFX_DEL  ---     0.494 */SLICE_328.C0 to *LICE_328.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2/SLICE_328
ROUTE         1   e 1.081 *LICE_328.OFX0 to */SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
CTOF_DEL    ---     0.260 */SLICE_123.C0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_32.Q0 to */SLICE_400.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_400.D0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_347.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_347.D0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_34.Q1 to */SLICE_400.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_400.A0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_347.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_347.D0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_33.Q0 to */SLICE_400.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_400.B0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_347.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_347.D0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_280 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_280.CLK to */SLICE_280.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_280 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_280.Q0 to */SLICE_327.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.A0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_283 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_283.CLK to */SLICE_283.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_283 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_283.Q0 to */SLICE_327.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
CTOOFX_DEL  ---     0.494 */SLICE_327.D1 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *u/SLICE_32.Q1 to */SLICE_401.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_401.A0 to */SLICE_401.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_401
ROUTE         3   e 1.081 */SLICE_401.F0 to */SLICE_347.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_11_1
CTOF_DEL    ---     0.260 */SLICE_347.A0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *u/SLICE_33.Q1 to */SLICE_400.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_400.C0 to */SLICE_400.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_400
ROUTE         5   e 1.081 */SLICE_400.F0 to */SLICE_347.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.260 */SLICE_347.D0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_398.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_398.D0 to */SLICE_398.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_398
ROUTE         9   e 1.081 */SLICE_398.F0 to */SLICE_347.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un3_jtdo
CTOF_DEL    ---     0.260 */SLICE_347.C0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_137.CLK to */SLICE_137.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_137.Q0 to */SLICE_329.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]
CTOOFX_DEL  ---     0.494 */SLICE_329.B1 to *LICE_329.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_RNIRJH44/SLICE_329
ROUTE         2   e 1.081 *LICE_329.OFX0 to */SLICE_415.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_1
CTOF_DEL    ---     0.260 */SLICE_415.C0 to */SLICE_415.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_415
ROUTE         1   e 1.081 */SLICE_415.F0 to */SLICE_406.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_13
CTOF_DEL    ---     0.260 */SLICE_406.D1 to */SLICE_406.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         1   e 1.081 */SLICE_406.F1 to */SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
CTOF_DEL    ---     0.260 */SLICE_123.D0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.075ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.982ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_327.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOOFX_DEL  ---     0.494 */SLICE_327.B0 to *LICE_327.OFX0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_327
ROUTE         1   e 1.081 *LICE_327.OFX0 to */SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.260 */SLICE_374.B0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.982   (27.7% logic, 72.3% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_185.CLK to */SLICE_185.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_185.Q1 to */SLICE_461.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[1]
CTOF_DEL    ---     0.260 */SLICE_461.A1 to */SLICE_461.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F1 to */SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.260 */SLICE_394.C0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_389.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_389.A0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_329.M0 top_reveal_coretop_instance/top_la0_inst_0/addr_15
MTOOFX_DEL  ---     0.260 */SLICE_329.M0 to *LICE_329.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_RNIRJH44/SLICE_329
ROUTE         2   e 1.081 *LICE_329.OFX0 to */SLICE_415.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_1
CTOF_DEL    ---     0.260 */SLICE_415.C0 to */SLICE_415.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_415
ROUTE         1   e 1.081 */SLICE_415.F0 to */SLICE_406.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_13
CTOF_DEL    ---     0.260 */SLICE_406.D1 to */SLICE_406.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         1   e 1.081 */SLICE_406.F1 to */SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
CTOF_DEL    ---     0.260 */SLICE_123.D0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_385.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_385.A0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_377.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_377.B1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_394.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_394.D0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_443.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_443.B1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_388.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_388.A0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_162.CLK to */SLICE_162.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_162.Q0 to */SLICE_545.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.260 */SLICE_545.C0 to */SLICE_545.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 1.081 */SLICE_545.F0 to */SLICE_376.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_3_5_0
CTOF_DEL    ---     0.260 */SLICE_376.A1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_390.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_390.A0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_387.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_387.A0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_391.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_391.A0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_174.CLK to */SLICE_174.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_174.Q1 to */SLICE_461.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]
CTOF_DEL    ---     0.260 */SLICE_461.D1 to */SLICE_461.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F1 to */SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.260 */SLICE_394.C0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_376.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_376.D1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_386.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_386.A0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_463.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_463.B1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_442.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_442.B1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_442.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_442.B0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_386.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_386.A0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_383.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_383.B0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_444.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_444.B1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_406.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_406.C0 to */SLICE_406.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_406
ROUTE         2   e 1.081 */SLICE_406.F0 to */SLICE_414.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_13_1_0
CTOF_DEL    ---     0.260 */SLICE_414.B0 to */SLICE_414.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_414
ROUTE         1   e 1.081 */SLICE_414.F0 to */SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5
CTOF_DEL    ---     0.260 */SLICE_411.B1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_456.CLK to */SLICE_456.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_456.Q0 to */SLICE_461.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.260 */SLICE_461.B1 to */SLICE_461.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F1 to */SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.260 */SLICE_394.C0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_549.CLK to */SLICE_549.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 (from ipClk_c)
ROUTE         5   e 1.081 */SLICE_549.Q0 to */SLICE_407.A1 top_reveal_coretop_instance/top_la0_inst_0/even_parity
CTOF_DEL    ---     0.260 */SLICE_407.A1 to */SLICE_407.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_407
ROUTE         2   e 1.081 */SLICE_407.F1 to */SLICE_414.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
CTOF_DEL    ---     0.260 */SLICE_414.A0 to */SLICE_414.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_414
ROUTE         1   e 1.081 */SLICE_414.F0 to */SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5
CTOF_DEL    ---     0.260 */SLICE_411.B1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_185.CLK to */SLICE_185.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_185 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_185.Q0 to */SLICE_405.C0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
CTOF_DEL    ---     0.260 */SLICE_405.C0 to */SLICE_405.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405
ROUTE         1   e 1.081 */SLICE_405.F0 to */SLICE_376.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/rd_dout_tm_m_1[0]
CTOF_DEL    ---     0.260 */SLICE_376.C1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_463.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_463.B0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_391.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_391.A0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_390.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_390.A0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_443.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_443.B0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_389.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_389.A0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_388.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_388.A0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_387.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_387.A0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_462.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_462.B0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_385.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_385.A0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_545.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_545.B0 to */SLICE_545.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 1.081 */SLICE_545.F0 to */SLICE_376.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_3_5_0
CTOF_DEL    ---     0.260 */SLICE_376.A1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_377.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_377.A1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_394.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_394.D0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_405.CLK to */SLICE_405.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_405.Q0 to */SLICE_461.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.260 */SLICE_461.C1 to */SLICE_461.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F1 to */SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.260 */SLICE_394.C0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_377.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_377.C1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_394.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_394.D0 to */SLICE_394.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         1   e 1.081 */SLICE_394.F0 to */SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
CTOF_DEL    ---     0.260 */SLICE_379.A0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_462.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_462.B1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_363.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_363.A0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_374.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_374.C0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_444.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_444.B0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_407.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_407.C1 to */SLICE_407.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_407
ROUTE         2   e 1.081 */SLICE_407.F1 to */SLICE_414.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
CTOF_DEL    ---     0.260 */SLICE_414.A0 to */SLICE_414.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_414
ROUTE         1   e 1.081 */SLICE_414.F0 to */SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5
CTOF_DEL    ---     0.260 */SLICE_411.B1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_315.CLK to */SLICE_315.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE        22   e 1.081 */SLICE_315.Q0 to */SLICE_375.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[0]
CTOF_DEL    ---     0.260 */SLICE_375.C1 to */SLICE_375.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_375
ROUTE         1   e 1.081 */SLICE_375.F1 to */SLICE_413.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_16
CTOF_DEL    ---     0.260 */SLICE_413.D0 to */SLICE_413.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_413
ROUTE         1   e 1.081 */SLICE_413.F0 to */SLICE_411.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_1
CTOF_DEL    ---     0.260 */SLICE_411.A1 to */SLICE_411.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_411
ROUTE         1   e 1.081 */SLICE_411.F1 to */SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
CTOF_DEL    ---     0.260 */SLICE_123.A0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_363.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_363.B0 to */SLICE_363.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_363
ROUTE         4   e 1.081 */SLICE_363.F0 to */SLICE_374.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.260 */SLICE_374.C0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.841ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (5.748ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    5.748   (24.8% logic, 75.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_367.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_367.C0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_449.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_449.A1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.731ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (5.487ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.487   (21.2% logic, 78.8% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.580ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.487ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_487.CLK to */SLICE_487.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487 (from ipClk_c)
ROUTE         2   e 0.280 */SLICE_487.Q0 to */SLICE_487.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]
CTOF_DEL    ---     0.260 */SLICE_487.D0 to */SLICE_487.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_487
ROUTE         1   e 1.081 */SLICE_487.F0 to */SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.260 */SLICE_364.A1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.487   (30.7% logic, 69.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.580ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (5.487ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_456.CLK to */SLICE_456.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (from jtaghub16_jtck)
ROUTE         4   e 0.280 */SLICE_456.Q0 to */SLICE_456.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.260 */SLICE_456.B1 to */SLICE_456.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456
ROUTE         1   e 1.081 */SLICE_456.F1 to */SLICE_403.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_115_0
CTOF_DEL    ---     0.260 */SLICE_403.B1 to */SLICE_403.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_403
ROUTE         1   e 1.081 */SLICE_403.F1 to */SLICE_409.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1_1
CTOF_DEL    ---     0.260 */SLICE_409.B1 to */SLICE_409.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_409
ROUTE         1   e 1.081 */SLICE_409.F1 to */SLICE_123.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1
CTOF_DEL    ---     0.260 */SLICE_123.B1 to */SLICE_123.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.280 */SLICE_123.F1 to */SLICE_123.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_1
CTOF_DEL    ---     0.260 */SLICE_123.B0 to */SLICE_123.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.487   (30.7% logic, 69.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.580ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_479 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (5.487ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_479.CLK to */SLICE_479.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_479 (from ipClk_c)
ROUTE         5   e 0.280 */SLICE_479.Q0 to */SLICE_479.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]
CTOF_DEL    ---     0.260 */SLICE_479.B0 to */SLICE_479.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/SLICE_479
ROUTE         1   e 1.081 */SLICE_479.F0 to */SLICE_364.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][2]
CTOF_DEL    ---     0.260 */SLICE_364.B1 to */SLICE_364.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_364
ROUTE         1   e 1.081 */SLICE_364.F1 to */SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.260 */SLICE_380.A1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    5.487   (30.7% logic, 69.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.580ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.487ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_366.CLK to */SLICE_366.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366 (from ipClk_c)
ROUTE         5   e 0.280 */SLICE_366.Q0 to */SLICE_366.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]
CTOF_DEL    ---     0.260 */SLICE_366.B0 to */SLICE_366.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 0.280 */SLICE_366.F0 to */SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.260 */SLICE_366.D1 to */SLICE_366.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_366
ROUTE         1   e 1.081 */SLICE_366.F1 to */SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
CTOF_DEL    ---     0.260 */SLICE_374.A0 to */SLICE_374.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_374
ROUTE         4   e 1.081 */SLICE_374.F0 to */SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.260 */SLICE_402.C1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.487   (30.7% logic, 69.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_544.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_544.B0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_544.A0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_544.A0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.470ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (5.226ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 0.280 */SLICE_397.F1 to */SLICE_397.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_397.D0 to */SLICE_397.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         1   e 1.081 */SLICE_397.F0 to */SLICE_344.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa_1
CTOF_DEL    ---     0.260 */SLICE_344.C1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    5.226   (27.2% logic, 72.8% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_272 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_272.CLK to */SLICE_272.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/SLICE_272 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_272.Q0 to */SLICE_460.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]
CTOF_DEL    ---     0.260 */SLICE_460.C1 to */SLICE_460.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F1 to */SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.260 */SLICE_381.A1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_405.CLK to */SLICE_405.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_405.Q0 to */SLICE_460.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.260 */SLICE_460.C0 to */SLICE_460.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F0 to */SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.260 */SLICE_381.C1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_175.CLK to */SLICE_175.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_175.Q0 to */SLICE_461.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]
CTOF_DEL    ---     0.260 */SLICE_461.D0 to */SLICE_461.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F0 to */SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.260 */SLICE_380.C1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_460.D1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_460.D1 to */SLICE_460.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F1 to */SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.260 */SLICE_381.A1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_405.CLK to */SLICE_405.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (from jtaghub16_jtck)
ROUTE         5   e 0.280 */SLICE_405.Q0 to */SLICE_405.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.260 */SLICE_405.D0 to */SLICE_405.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405
ROUTE         1   e 1.081 */SLICE_405.F0 to */SLICE_376.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/rd_dout_tm_m_1[0]
CTOF_DEL    ---     0.260 */SLICE_376.C1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_456.CLK to */SLICE_456.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_456.Q0 to */SLICE_461.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.260 */SLICE_461.B0 to */SLICE_461.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F0 to */SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.260 */SLICE_380.C1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_460.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_460.A1 to */SLICE_460.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F1 to */SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.260 */SLICE_381.A1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_464.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_464.D1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_186 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_186.CLK to */SLICE_186.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_186 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_186.Q1 to */SLICE_460.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[3]
CTOF_DEL    ---     0.260 */SLICE_460.A0 to */SLICE_460.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F0 to */SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.260 */SLICE_381.C1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_186 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_186.CLK to */SLICE_186.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_186 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_186.Q0 to */SLICE_461.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[2]
CTOF_DEL    ---     0.260 */SLICE_461.A0 to */SLICE_461.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F0 to */SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.260 */SLICE_380.C1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_460.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_460.B1 to */SLICE_460.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F1 to */SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.260 */SLICE_381.A1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_464.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_464.D0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_456.CLK to */SLICE_456.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_456.Q0 to */SLICE_460.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.260 */SLICE_460.B0 to */SLICE_460.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F0 to */SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.260 */SLICE_381.C1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_376.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_376.D0 to */SLICE_376.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 0.280 */SLICE_376.F0 to */SLICE_376.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtdo_iv_N_2L1_RNI0K811
CTOF_DEL    ---     0.260 */SLICE_376.B1 to */SLICE_376.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_376
ROUTE         1   e 1.081 */SLICE_376.F1 to */SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
CTOF_DEL    ---     0.260 */SLICE_402.B1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_405.CLK to */SLICE_405.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_405.Q0 to */SLICE_461.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.260 */SLICE_461.C0 to */SLICE_461.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_461
ROUTE         1   e 1.081 */SLICE_461.F0 to */SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.260 */SLICE_380.C1 to */SLICE_380.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 0.280 */SLICE_380.F1 to */SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
CTOF_DEL    ---     0.260 */SLICE_380.A0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_382.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_382.B1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 0.280 */SLICE_382.F1 to */SLICE_382.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_382.B0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_175.CLK to */SLICE_175.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_175.Q1 to */SLICE_460.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]
CTOF_DEL    ---     0.260 */SLICE_460.D0 to */SLICE_460.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_460
ROUTE         1   e 1.081 */SLICE_460.F0 to */SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.260 */SLICE_381.C1 to */SLICE_381.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 0.280 */SLICE_381.F1 to */SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.260 */SLICE_381.A0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.040ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.947ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.947   (28.8% logic, 71.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_485.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_485.D0 to */SLICE_485.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_485
ROUTE         1   e 1.081 */SLICE_485.F0 to */SLICE_368.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3
CTOF_DEL    ---     0.260 */SLICE_368.C1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_485.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_485.A0 to */SLICE_485.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_485
ROUTE         1   e 1.081 */SLICE_485.F0 to */SLICE_368.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3
CTOF_DEL    ---     0.260 */SLICE_368.C1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_211.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_211.C1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_485.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_485.C0 to */SLICE_485.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_485
ROUTE         1   e 1.081 */SLICE_485.F0 to */SLICE_368.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3
CTOF_DEL    ---     0.260 */SLICE_368.C1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_485.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_485.B0 to */SLICE_485.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_485
ROUTE         1   e 1.081 */SLICE_485.F0 to */SLICE_368.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3
CTOF_DEL    ---     0.260 */SLICE_368.C1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_370.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_370.C1 to */SLICE_370.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370
ROUTE         3   e 1.081 */SLICE_370.F1 to */SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
CTOF_DEL    ---     0.260 */SLICE_369.A0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_378.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_378.A1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_211.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_211.C1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_211.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_211.C1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F1 to */SLICE_368.D1 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_368.D1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.930ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.686ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 0.280 */SLICE_396.F1 to */SLICE_396.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_396.B0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.686   (24.8% logic, 75.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_323.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_323.A0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_464.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_464.C0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_464.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_464.A0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_123.CLK to */SLICE_123.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_123.Q0 to */SLICE_347.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc
CTOF_DEL    ---     0.260 */SLICE_347.B0 to */SLICE_347.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_347
ROUTE         3   e 1.081 */SLICE_347.F0 to */SLICE_330.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g1_3_0
CTOOFX_DEL  ---     0.494 */SLICE_330.A0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_321.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_321.A0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_321.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_321.A0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_323.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_323.A0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_394.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_394.A1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_318.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_318.A0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q1 to */SLICE_464.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[11]
CTOF_DEL    ---     0.260 */SLICE_464.B1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_394.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_394.B1 to */SLICE_394.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_394
ROUTE         7   e 1.081 */SLICE_394.F1 to */SLICE_446.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg25_sn
CTOF_DEL    ---     0.260 */SLICE_446.A0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_318.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_318.A0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_247.CLK to */SLICE_247.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_247.Q0 to */SLICE_412.D1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.260 */SLICE_412.D1 to */SLICE_412.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412
ROUTE         3   e 1.081 */SLICE_412.F1 to */SLICE_330.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/trace_dout_RNI4TQC1[0]
CTOOFX_DEL  ---     0.494 */SLICE_330.C1 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to */SLICE_464.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[10]
CTOF_DEL    ---     0.260 */SLICE_464.A1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_464.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_464.B0 to */SLICE_464.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F0 to */SLICE_379.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1
CTOF_DEL    ---     0.260 */SLICE_379.C1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.734ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (4.641ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_134.Q1 to */SLICE_464.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]
CTOF_DEL    ---     0.260 */SLICE_464.C1 to */SLICE_464.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_464
ROUTE         1   e 1.081 */SLICE_464.F1 to */SLICE_379.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1_0
CTOF_DEL    ---     0.260 */SLICE_379.D1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    4.641   (30.1% logic, 69.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_385.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_385.A0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_383.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_383.B0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_391.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_391.A0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_463.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_463.A1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_462.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_462.A0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_463.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_463.A0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_390.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_390.A0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_389.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_389.A0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_389.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_389.A0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_443.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_443.B0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_443.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_443.A0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_388.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_388.A0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_388.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_388.A0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_443.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_443.B1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_443.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_443.A1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_386.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_386.A0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_462.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_462.A1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_442.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_442.A1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_387.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_387.A0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_442.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_442.A0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_444.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_444.A0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_444.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_444.A1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_444.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_444.B0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_391.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_391.A0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_463.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_463.B0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_390.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_390.A0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_463.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_463.B1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_462.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_462.B1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_442.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_442.B1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_387.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_387.A0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_442.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_442.B0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_386.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_386.A0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_382.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_382.A0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_385.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_385.D0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_443.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_443.A1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_491.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_491.B0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_492.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_492.B0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_493.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_493.B0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_494.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_494.B0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_495.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_495.B0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_496.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_496.B0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_497.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_497.B0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_498.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_498.B0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_499.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_499.B0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_500.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_500.B0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_501.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_501.B0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_502.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_502.B0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_503.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_503.B0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_504.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_504.B0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_505.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_505.B0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_506.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_506.B0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_507.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_507.B0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_508.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_508.B0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_509.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_509.B0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_510.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_510.B0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_511.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_511.B0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_512.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_512.B0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_513.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_513.B0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_514.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_514.B0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_515.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_515.B0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_516.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_516.B0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_517.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_517.B0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_518.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_518.B0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_519.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_519.B0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_535.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_535.B0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_391.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_391.D0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_391.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_391.A0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_463.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_463.A0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_520.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_520.B0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_521.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_521.B0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_534.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_534.B0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_390.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_390.D0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_390.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_390.A0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_463.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_463.A1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_522.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_522.B0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_380.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_380.C0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_444.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_444.A1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_527.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_527.B0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_490.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_490.C0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_526.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_526.B0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_462.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_462.A1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_437.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_437.D1 to */SLICE_437.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         1   e 1.081 */SLICE_437.F1 to */SLICE_402.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0_2
CTOF_DEL    ---     0.260 */SLICE_402.A1 to */SLICE_402.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_402
ROUTE         2   e 1.081 */SLICE_402.F1 to */SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
CTOF_DEL    ---     0.260 */SLICE_162.D0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_178.CLK to */SLICE_178.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_178.Q1 to */SLICE_377.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]
CTOF_DEL    ---     0.260 */SLICE_377.B0 to */SLICE_377.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE         1   e 1.081 */SLICE_377.F0 to */SLICE_490.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[8]
CTOF_DEL    ---     0.260 */SLICE_490.A0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_442.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_442.A1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_532.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_532.B0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_387.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_387.D0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_387.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_387.A0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_442.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_442.A0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_533.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_533.B0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_531.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_531.B0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_530.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_530.B0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_529.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_529.B0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_386.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_386.D0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_386.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_386.A0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_382.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_382.A0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_528.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_528.B0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_385.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_385.A0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_385.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_385.A0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_462.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_462.B0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_462.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_462.A0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_384.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_384.C0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_382.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_382.D1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_383.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_383.B0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_524.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_524.B0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_381.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_381.C0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q1 to */SLICE_396.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.260 */SLICE_396.C1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_424.C1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_424.C1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_172.CLK to */SLICE_172.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_172.Q0 to */SLICE_396.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.260 */SLICE_396.B1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_288.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_288.D1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_289.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_289.D0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_291.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_291.D0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_290.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_290.D0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_171.Q1 to */SLICE_396.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.260 */SLICE_396.A1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_173.Q0 to */SLICE_396.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.260 */SLICE_396.D1 to */SLICE_396.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         2   e 1.081 */SLICE_396.F1 to */SLICE_393.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.260 */SLICE_393.A1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_444.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_444.A0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_525.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_525.B0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 1.081 */SLICE_382.F1 to */SLICE_444.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_444.B1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_302.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_302.B0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_287.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_287.D0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_285.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_285.D0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_284.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_284.D1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_389.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_389.D0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_389.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_389.A0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_443.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_443.A0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_523.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_523.B0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_388.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_388.D0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_388.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.260 */SLICE_388.A0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.500ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.407ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 1.081 */SLICE_304.F1 to */SLICE_286.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_286.D0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    4.407   (26.4% logic, 73.6% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_396.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_396.C0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_181.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_180.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_367.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_367.A0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_396.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_396.C0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_396.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_396.C0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_179.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_178.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_177.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_176.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_175.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_538.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_538.B0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_174.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_215.A1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_215.A1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_215.A1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_215.A1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_211.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[15]
CTOF_DEL    ---     0.260 */SLICE_211.A0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_367.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_367.A0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_396.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_396.D0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_396.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_396.D0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_396.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_396.D0 to */SLICE_396.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_396
ROUTE         1   e 1.081 */SLICE_396.F0 to */SLICE_378.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1078
CTOF_DEL    ---     0.260 */SLICE_378.A0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_181.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_180.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_179.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_178.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_176.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_175.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_174.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_211.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[15]
CTOF_DEL    ---     0.260 */SLICE_211.A0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_538.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_538.D0 to */SLICE_538.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 1.081 */SLICE_538.F0 to */SLICE_392.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_87
CTOF_DEL    ---     0.260 */SLICE_392.A0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_177.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.390ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (4.146ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_424.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_424.A0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.146   (21.8% logic, 78.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.129ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (3.885ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 1.081 */SLICE_397.F1 to */SLICE_112.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_112.D0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.280 */SLICE_112.F0 to */SLICE_112.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_112.B1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.885   (29.9% logic, 70.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.129ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (3.885ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 1.081 */SLICE_397.F1 to */SLICE_112.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_112.D0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.280 */SLICE_112.F0 to */SLICE_112.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_112.B1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.885   (29.9% logic, 70.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.129ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.885ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_211.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_211.C1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    3.885   (29.9% logic, 70.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.083ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.990ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *u/SLICE_36.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
C0TOFCO_DE  ---     0.790 *u/SLICE_36.A0 to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_35.FCI to *u/SLICE_35.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F1 to */SLICE_215.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.260 */SLICE_215.D0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.990   (45.8% logic, 54.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.995ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.902ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *u/SLICE_36.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
C0TOFCO_DE  ---     0.790 *u/SLICE_36.A0 to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_35.FCI to *u/SLICE_35.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F0 to */SLICE_214.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.260 */SLICE_214.D1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.902   (44.5% logic, 55.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.850ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.757ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *u/SLICE_37.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_37.A1 to */SLICE_37.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_36.FCI to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_35.FCI to *u/SLICE_35.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F1 to */SLICE_215.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.260 */SLICE_215.D0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.757   (42.4% logic, 57.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.850ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (3.757ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_30.A1 to */SLICE_30.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 0.001 */SLICE_30.FCO to */SLICE_29.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_29.FCI to */SLICE_29.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_29
ROUTE         1   e 0.001 */SLICE_29.FCO to */SLICE_28.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_28.FCI to *u/SLICE_28.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_28
ROUTE         1   e 1.081 *u/SLICE_28.F1 to */SLICE_173.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4]
CTOF_DEL    ---     0.260 */SLICE_173.C0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.757   (42.4% logic, 57.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.844ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (3.751ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_30.A1 to */SLICE_30.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 0.001 */SLICE_30.FCO to */SLICE_29.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_29.FCI to */SLICE_29.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_29
ROUTE         1   e 0.001 */SLICE_29.FCO to */SLICE_28.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOFCO_D  ---     0.081 */SLICE_28.FCI to */SLICE_28.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_28
ROUTE         1   e 0.001 */SLICE_28.FCO to */SLICE_27.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_27.FCI to *u/SLICE_27.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_27
ROUTE         1   e 1.081 *u/SLICE_27.F0 to */SLICE_173.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5]
CTOF_DEL    ---     0.260 */SLICE_173.C1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.751   (42.3% logic, 57.7% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.768ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.675ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q0 to *u/SLICE_36.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
C1TOFCO_DE  ---     0.475 *u/SLICE_36.A1 to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_35.FCI to *u/SLICE_35.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F1 to */SLICE_215.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.260 */SLICE_215.D0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.675   (41.1% logic, 58.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.768ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (3.675ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_30.A1 to */SLICE_30.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 0.001 */SLICE_30.FCO to */SLICE_29.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0]
FCITOF1_DE  ---     0.393 */SLICE_29.FCI to *u/SLICE_29.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_29
ROUTE         1   e 1.081 *u/SLICE_29.F1 to */SLICE_172.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2]
CTOF_DEL    ---     0.260 */SLICE_172.C0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.675   (41.1% logic, 58.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.768ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.675ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *u/SLICE_37.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_37.A1 to */SLICE_37.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOF1_DE  ---     0.393 */SLICE_36.FCI to *u/SLICE_36.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 1.081 *u/SLICE_36.F1 to */SLICE_214.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.260 */SLICE_214.D0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.675   (41.1% logic, 58.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.762ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.669ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *u/SLICE_37.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_37.A1 to */SLICE_37.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_36.FCI to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_35.FCI to *u/SLICE_35.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F0 to */SLICE_214.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.260 */SLICE_214.D1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.669   (41.0% logic, 59.0% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.762ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (3.669ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_30.A1 to */SLICE_30.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 0.001 */SLICE_30.FCO to */SLICE_29.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_29.FCI to */SLICE_29.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_29
ROUTE         1   e 0.001 */SLICE_29.FCO to */SLICE_28.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_28.FCI to *u/SLICE_28.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_28
ROUTE         1   e 1.081 *u/SLICE_28.F0 to */SLICE_172.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3]
CTOF_DEL    ---     0.260 */SLICE_172.C1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.669   (41.0% logic, 59.0% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_188 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_188.CLK to */SLICE_188.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_188 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_188.Q0 to */SLICE_386.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[6]
CTOF_DEL    ---     0.260 */SLICE_386.A1 to */SLICE_386.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 0.280 */SLICE_386.F1 to */SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.260 */SLICE_386.B0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_189.CLK to */SLICE_189.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_189.Q0 to */SLICE_390.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
CTOF_DEL    ---     0.260 */SLICE_390.A1 to */SLICE_390.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 0.280 */SLICE_390.F1 to */SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.260 */SLICE_390.B0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_187.CLK to */SLICE_187.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_187.Q0 to */SLICE_384.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[4]
CTOF_DEL    ---     0.260 */SLICE_384.A1 to */SLICE_384.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 0.280 */SLICE_384.F1 to */SLICE_384.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[3]
CTOF_DEL    ---     0.260 */SLICE_384.A0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_189.CLK to */SLICE_189.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_189.Q0 to */SLICE_388.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
CTOF_DEL    ---     0.260 */SLICE_388.A1 to */SLICE_388.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 0.280 */SLICE_388.F1 to */SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.260 */SLICE_388.B0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q0 to */SLICE_450.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.260 */SLICE_450.D0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_386.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_386.C1 to */SLICE_386.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 0.280 */SLICE_386.F1 to */SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.260 */SLICE_386.B0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_176.CLK to */SLICE_176.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_176.Q1 to */SLICE_385.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]
CTOF_DEL    ---     0.260 */SLICE_385.D1 to */SLICE_385.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 0.280 */SLICE_385.F1 to */SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.260 */SLICE_385.B0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q0 to */SLICE_450.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.260 */SLICE_450.C1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_180.CLK to */SLICE_180.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_180.Q1 to */SLICE_390.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]
CTOF_DEL    ---     0.260 */SLICE_390.D1 to */SLICE_390.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 0.280 */SLICE_390.F1 to */SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.260 */SLICE_390.B0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_179.CLK to */SLICE_179.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_179.Q0 to */SLICE_388.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]
CTOF_DEL    ---     0.260 */SLICE_388.D1 to */SLICE_388.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 0.280 */SLICE_388.F1 to */SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.260 */SLICE_388.B0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q1 to */SLICE_450.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.260 */SLICE_450.C0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q0 to */SLICE_450.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.260 */SLICE_450.A0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q0 to */SLICE_484.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.260 */SLICE_484.B0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_391.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_391.B1 to */SLICE_391.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 0.280 */SLICE_391.F1 to */SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.260 */SLICE_391.B0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_391.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_391.C1 to */SLICE_391.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 0.280 */SLICE_391.F1 to */SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.260 */SLICE_391.B0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_389.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_389.C1 to */SLICE_389.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 0.280 */SLICE_389.F1 to */SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.260 */SLICE_389.B0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_382.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_382.A1 to */SLICE_382.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE        12   e 0.280 */SLICE_382.F1 to */SLICE_382.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1116
CTOF_DEL    ---     0.260 */SLICE_382.B0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_176.CLK to */SLICE_176.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_176.Q0 to */SLICE_384.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.260 */SLICE_384.C1 to */SLICE_384.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 0.280 */SLICE_384.F1 to */SLICE_384.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[3]
CTOF_DEL    ---     0.260 */SLICE_384.A0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_134.CLK to */SLICE_134.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_134.Q0 to */SLICE_377.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]
CTOF_DEL    ---     0.260 */SLICE_377.C1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_182.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_182.A1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q1 to */SLICE_377.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]
CTOF_DEL    ---     0.260 */SLICE_377.B1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_182.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_182.A1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_544.A0 top_reveal_coretop_instance/top_la0_inst_0/parity_err
CTOF_DEL    ---     0.260 */SLICE_544.A0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_459.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_459.C0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_410.CLK to */SLICE_410.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_410.Q0 to */SLICE_459.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast
CTOF_DEL    ---     0.260 */SLICE_459.A0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_389.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_389.B1 to */SLICE_389.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 0.280 */SLICE_389.F1 to */SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.260 */SLICE_389.B0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_387.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_387.B1 to */SLICE_387.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 0.280 */SLICE_387.F1 to */SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.260 */SLICE_387.B0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q0 to */SLICE_484.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.260 */SLICE_484.D0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q0 to */SLICE_450.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.260 */SLICE_450.A1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q1 to */SLICE_449.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.260 */SLICE_449.C0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_387.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_387.C1 to */SLICE_387.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 0.280 */SLICE_387.F1 to */SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.260 */SLICE_387.B0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_189.CLK to */SLICE_189.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_189.Q1 to */SLICE_389.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
CTOF_DEL    ---     0.260 */SLICE_389.A1 to */SLICE_389.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 0.280 */SLICE_389.F1 to */SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.260 */SLICE_389.B0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_187.CLK to */SLICE_187.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_187.Q1 to */SLICE_385.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.260 */SLICE_385.A1 to */SLICE_385.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 0.280 */SLICE_385.F1 to */SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.260 */SLICE_385.B0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_189.CLK to */SLICE_189.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 (from ipClk_c)
ROUTE         3   e 1.081 */SLICE_189.Q0 to */SLICE_391.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
CTOF_DEL    ---     0.260 */SLICE_391.A1 to */SLICE_391.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 0.280 */SLICE_391.F1 to */SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.260 */SLICE_391.B0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_187.CLK to */SLICE_187.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_187 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_187.Q1 to */SLICE_387.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.260 */SLICE_387.A1 to */SLICE_387.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 0.280 */SLICE_387.F1 to */SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.260 */SLICE_387.B0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_285.CLK to */SLICE_285.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_285.Q1 to */SLICE_450.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.260 */SLICE_450.B0 to */SLICE_450.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F0 to */SLICE_304.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.260 */SLICE_304.C1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_179.CLK to */SLICE_179.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_179.Q1 to */SLICE_389.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.260 */SLICE_389.D1 to */SLICE_389.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 0.280 */SLICE_389.F1 to */SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.260 */SLICE_389.B0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_133.CLK to */SLICE_133.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_133.Q0 to */SLICE_377.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]
CTOF_DEL    ---     0.260 */SLICE_377.A1 to */SLICE_377.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_377
ROUTE        11   e 1.081 */SLICE_377.F1 to */SLICE_182.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_0_sqmuxa_sn
CTOF_DEL    ---     0.260 */SLICE_182.A1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_178.CLK to */SLICE_178.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_178.Q0 to */SLICE_387.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]
CTOF_DEL    ---     0.260 */SLICE_387.D1 to */SLICE_387.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 0.280 */SLICE_387.F1 to */SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.260 */SLICE_387.B0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_211.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_211.B1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_287.CLK to */SLICE_287.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_287.Q1 to */SLICE_450.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.260 */SLICE_450.D1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_286.CLK to */SLICE_286.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_286.Q1 to */SLICE_450.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.260 */SLICE_450.B1 to */SLICE_450.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_450
ROUTE         1   e 1.081 */SLICE_450.F1 to */SLICE_304.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.260 */SLICE_304.B1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_112.Q0 to */SLICE_459.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_459.B0 to */SLICE_459.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459
ROUTE         2   e 1.081 */SLICE_459.F0 to */SLICE_211.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block
CTOF_DEL    ---     0.260 */SLICE_211.A1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_289.CLK to */SLICE_289.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_289.Q1 to */SLICE_484.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.260 */SLICE_484.C0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_291.CLK to */SLICE_291.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_291.Q1 to */SLICE_449.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.260 */SLICE_449.D0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_385.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_385.B1 to */SLICE_385.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 0.280 */SLICE_385.F1 to */SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.260 */SLICE_385.B0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_385.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_385.C1 to */SLICE_385.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 0.280 */SLICE_385.F1 to */SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.260 */SLICE_385.B0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 0.280 */SLICE_379.F1 to */SLICE_379.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.260 */SLICE_379.C0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 0.280 */SLICE_383.F1 to */SLICE_383.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.260 */SLICE_383.A0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 0.280 */SLICE_393.F1 to */SLICE_393.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_393.B0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_181.CLK to */SLICE_181.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_181.Q1 to */SLICE_391.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]
CTOF_DEL    ---     0.260 */SLICE_391.D1 to */SLICE_391.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 0.280 */SLICE_391.F1 to */SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.260 */SLICE_391.B0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_390.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_390.C1 to */SLICE_390.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 0.280 */SLICE_390.F1 to */SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.260 */SLICE_390.B0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_390.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_390.B1 to */SLICE_390.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 0.280 */SLICE_390.F1 to */SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.260 */SLICE_390.B0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_177.CLK to */SLICE_177.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_177.Q0 to */SLICE_386.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]
CTOF_DEL    ---     0.260 */SLICE_386.D1 to */SLICE_386.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 0.280 */SLICE_386.F1 to */SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.260 */SLICE_386.B0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_290.CLK to */SLICE_290.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_290.Q0 to */SLICE_449.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.260 */SLICE_449.B0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_388.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_388.B1 to */SLICE_388.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 0.280 */SLICE_388.F1 to */SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.260 */SLICE_388.B0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_284.CLK to */SLICE_284.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_284.Q1 to */SLICE_484.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.260 */SLICE_484.A0 to */SLICE_484.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_484
ROUTE         1   e 1.081 */SLICE_484.F0 to */SLICE_304.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.260 */SLICE_304.A1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_388.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_388.C1 to */SLICE_388.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 0.280 */SLICE_388.F1 to */SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.260 */SLICE_388.B0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_288.CLK to */SLICE_288.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_288.Q0 to */SLICE_449.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.260 */SLICE_449.A0 to */SLICE_449.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         1   e 1.081 */SLICE_449.F0 to */SLICE_304.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.260 */SLICE_304.D1 to */SLICE_304.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE        20   e 0.280 */SLICE_304.F1 to */SLICE_304.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.260 */SLICE_304.B0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_386.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_386.B1 to */SLICE_386.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 0.280 */SLICE_386.F1 to */SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.260 */SLICE_386.B0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.699ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (3.606ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_548.CLK to */SLICE_548.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_548.Q0 to */SLICE_544.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.260 */SLICE_544.B0 to */SLICE_544.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 1.081 */SLICE_544.F0 to */SLICE_211.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_jtck_0
CTOF_DEL    ---     0.260 */SLICE_211.D1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.606   (32.3% logic, 67.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.680ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.587ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q0 to *u/SLICE_36.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
C1TOFCO_DE  ---     0.475 *u/SLICE_36.A1 to */SLICE_36.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_35.FCI to *u/SLICE_35.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F0 to */SLICE_214.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.260 */SLICE_214.D1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.587   (39.7% logic, 60.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.680ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.587ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_30.A1 to */SLICE_30.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 0.001 */SLICE_30.FCO to */SLICE_29.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0]
FCITOF0_DE  ---     0.305 */SLICE_29.FCI to *u/SLICE_29.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_29
ROUTE         1   e 1.081 *u/SLICE_29.F0 to */SLICE_171.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1]
CTOF_DEL    ---     0.260 */SLICE_171.D1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.587   (39.7% logic, 60.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.680ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.587ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *u/SLICE_37.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_37.A1 to */SLICE_37.FCO top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOF0_DE  ---     0.305 */SLICE_36.FCI to *u/SLICE_36.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 1.081 *u/SLICE_36.F0 to */SLICE_213.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1]
CTOF_DEL    ---     0.260 */SLICE_213.D1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.587   (39.7% logic, 60.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_369.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_369.C0 to */SLICE_369.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 0.280 */SLICE_369.F0 to */SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
CTOF_DEL    ---     0.260 */SLICE_369.C1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_378.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_378.B1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_378.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_378.B1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_378.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_378.B1 to */SLICE_378.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         1   e 0.280 */SLICE_378.F1 to */SLICE_378.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din_0_sqmuxa_i_o4
CTOF_DEL    ---     0.260 */SLICE_378.B0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_139.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_190 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_190.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_157.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_156.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_155.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_154.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_149.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_146.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_145.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_133.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_144.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_143.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_142.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_141.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_405.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_138.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_97.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_148.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_147.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_153.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_128.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_152.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_151.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_99.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_137.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_31.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_32.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_33.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_34.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_456.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_136.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_140.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_150.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_160.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_96.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_159.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_158.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_94.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_367.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_367.A0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_368.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_368.B1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_178.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_174.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_215.A1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_215.A1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_176.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_180.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_367.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_367.B1 to */SLICE_367.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 0.280 */SLICE_367.F1 to */SLICE_367.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_96
CTOF_DEL    ---     0.260 */SLICE_367.B0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_141.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_159.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_158.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_157.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_156.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_155.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_154.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_31.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_32.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_33.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_34.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_135.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_150.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_160.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_153.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_152.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_145.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_149.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 0.280 */SLICE_304.Q0 to */SLICE_304.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_304.C0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 1.081 */SLICE_304.F0 to */SLICE_369.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_369.D1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_143.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_142.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_345.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_100.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_98.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_127.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_95.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_463.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_140.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_139.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_138.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_137.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_190 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_190.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_151.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_148.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_147.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_146.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_344.A1 to */SLICE_344.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         1   e 0.280 */SLICE_344.F1 to */SLICE_344.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_344.D0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.280 */SLICE_107.F0 to */SLICE_107.B1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_107.B1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_134.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 0.280 */SLICE_395.F1 to */SLICE_395.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_395.A0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_144.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_181.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_211.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[15]
CTOF_DEL    ---     0.260 */SLICE_211.A0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 1.081 */SLICE_211.F0 to */SLICE_215.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_215.D1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_175.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_179.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_367.A1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_367.A1 to */SLICE_367.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 0.280 */SLICE_367.F1 to */SLICE_367.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_96
CTOF_DEL    ---     0.260 */SLICE_367.B0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 0.280 */SLICE_392.F1 to */SLICE_392.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_392.B0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_177.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_368.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_368.A1 to */SLICE_368.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 0.280 */SLICE_368.F1 to */SLICE_368.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_62
CTOF_DEL    ---     0.260 */SLICE_368.A0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.589ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (3.345ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_449.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_449.B1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    3.345   (27.0% logic, 73.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_321.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_321.A0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_321.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_321.A1 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_318.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_318.A0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_318.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_318.A1 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_137.CLK to */SLICE_137.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_137.Q0 to */SLICE_330.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]
CTOOFX_DEL  ---     0.494 */SLICE_330.B1 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_188 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_188.CLK to */SLICE_188.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_188 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_188.Q1 to */SLICE_536.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[7]
CTOF_DEL    ---     0.260 */SLICE_536.A0 to */SLICE_536.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_536
ROUTE         1   e 1.081 */SLICE_536.F0 to */SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOOFX_DEL  ---     0.494 */SLICE_318.B0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_537.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_537.C0 to */SLICE_537.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         1   e 1.081 */SLICE_537.F0 to */SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOOFX_DEL  ---     0.494 */SLICE_321.B0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_536.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_536.B0 to */SLICE_536.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_536
ROUTE         1   e 1.081 */SLICE_536.F0 to */SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOOFX_DEL  ---     0.494 */SLICE_318.B0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_383.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_383.B1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_323.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_323.A1 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_540.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_540.B0 to */SLICE_540.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 1.081 */SLICE_540.F0 to */SLICE_323.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[13]
CTOOFX_DEL  ---     0.494 */SLICE_323.B0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_536.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_536.C0 to */SLICE_536.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_536
ROUTE         1   e 1.081 */SLICE_536.F0 to */SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOOFX_DEL  ---     0.494 */SLICE_318.B0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_540.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_540.A0 to */SLICE_540.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 1.081 */SLICE_540.F0 to */SLICE_323.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[13]
CTOOFX_DEL  ---     0.494 */SLICE_323.B0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_446.D0 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_446.D0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_323.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_323.A0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_537.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_537.B0 to */SLICE_537.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         1   e 1.081 */SLICE_537.F0 to */SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOOFX_DEL  ---     0.494 */SLICE_321.B0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_379.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[8]
CTOF_DEL    ---     0.260 */SLICE_379.A1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_181.CLK to */SLICE_181.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_181.Q0 to */SLICE_540.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]
CTOF_DEL    ---     0.260 */SLICE_540.C0 to */SLICE_540.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 1.081 */SLICE_540.F0 to */SLICE_323.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[13]
CTOOFX_DEL  ---     0.494 */SLICE_323.B0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_321.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_321.A0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_180.CLK to */SLICE_180.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_180.Q0 to */SLICE_537.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]
CTOF_DEL    ---     0.260 */SLICE_537.D0 to */SLICE_537.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         1   e 1.081 */SLICE_537.F0 to */SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOOFX_DEL  ---     0.494 */SLICE_321.B0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_321.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_321.A1 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_323.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_323.D0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_321.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_321.D0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_318.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_318.A0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_318.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_318.A0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_177.CLK to */SLICE_177.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_177.Q1 to */SLICE_536.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]
CTOF_DEL    ---     0.260 */SLICE_536.D0 to */SLICE_536.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_536
ROUTE         1   e 1.081 */SLICE_536.F0 to */SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOOFX_DEL  ---     0.494 */SLICE_318.B0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_321.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_321.A0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_446.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_446.B0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_323.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_323.A0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 1.081 *u/SLICE_97.Q1 to */SLICE_379.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[9]
CTOF_DEL    ---     0.260 */SLICE_379.B1 to */SLICE_379.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE        18   e 1.081 */SLICE_379.F1 to */SLICE_318.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOOFX_DEL  ---     0.494 */SLICE_318.D0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_318.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_318.A1 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_446.C0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_446.C0 to */SLICE_446.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_446
ROUTE        10   e 1.081 */SLICE_446.F0 to */SLICE_323.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOOFX_DEL  ---     0.494 */SLICE_323.A0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_315.CLK to */SLICE_315.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE        22   e 1.081 */SLICE_315.Q0 to */SLICE_330.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[0]
CTOOFX_DEL  ---     0.494 */SLICE_330.C0 to *LICE_330.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]/SLICE_330
ROUTE         1   e 1.081 *LICE_330.OFX0 to */SLICE_162.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_1[0]
CTOF_DEL    ---     0.260 */SLICE_162.C0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_189.CLK to */SLICE_189.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_189 (from ipClk_c)
ROUTE         2   e 1.081 */SLICE_189.Q1 to */SLICE_537.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
CTOF_DEL    ---     0.260 */SLICE_537.A0 to */SLICE_537.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         1   e 1.081 */SLICE_537.F0 to */SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOOFX_DEL  ---     0.494 */SLICE_321.B0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.393ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.300ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_383.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_383.D1 to */SLICE_383.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE        15   e 1.081 */SLICE_383.F1 to */SLICE_323.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_99
CTOOFX_DEL  ---     0.494 */SLICE_323.A1 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.300   (34.5% logic, 65.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.292ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.199ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q1 to *u/SLICE_35.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]
CTOF1_DEL   ---     0.393 *u/SLICE_35.A0 to *u/SLICE_35.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F1 to */SLICE_215.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.260 */SLICE_215.D0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.199   (32.4% logic, 67.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.292ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.199ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *u/SLICE_36.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
CTOF1_DEL   ---     0.393 *u/SLICE_36.A0 to *u/SLICE_36.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 1.081 *u/SLICE_36.F1 to */SLICE_214.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.260 */SLICE_214.D0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.199   (32.4% logic, 67.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_437.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_437.A0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_171.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.260 */SLICE_171.C1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_437.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_437.A0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_171.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.260 */SLICE_171.C0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_437.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_437.D0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_171.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.260 */SLICE_171.C0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *u/SLICE_37.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
CTOF_DEL    ---     0.260 *u/SLICE_37.A1 to *u/SLICE_37.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_37
ROUTE         1   e 1.081 *u/SLICE_37.F1 to */SLICE_213.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0]
CTOF_DEL    ---     0.260 */SLICE_213.D0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_124.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_124.C0 to */SLICE_124.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_184.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_184.B0 to */SLICE_184.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184
ROUTE         1   e 0.001 */SLICE_184.F0 to *SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_184.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_184.B0 to */SLICE_184.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184
ROUTE         1   e 0.001 */SLICE_184.F0 to *SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to */SLICE_393.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 */SLICE_393.B1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_160.CLK to */SLICE_160.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_160.Q0 to */SLICE_491.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]
CTOF_DEL    ---     0.260 */SLICE_491.A0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_158.CLK to */SLICE_158.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_158.Q1 to */SLICE_494.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]
CTOF_DEL    ---     0.260 */SLICE_494.A0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_159.CLK to */SLICE_159.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_159.Q0 to */SLICE_493.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]
CTOF_DEL    ---     0.260 */SLICE_493.A0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_157.CLK to */SLICE_157.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_157.Q0 to */SLICE_497.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]
CTOF_DEL    ---     0.260 */SLICE_497.A0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_156.CLK to */SLICE_156.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_156.Q1 to */SLICE_498.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]
CTOF_DEL    ---     0.260 */SLICE_498.A0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_445.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_445.D0 to */SLICE_445.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_445
ROUTE        16   e 1.081 */SLICE_445.F0 to */SLICE_323.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_55
MTOOFX_DEL  ---     0.260 */SLICE_323.M0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_144.CLK to */SLICE_144.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_144.Q0 to */SLICE_521.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]
CTOF_DEL    ---     0.260 */SLICE_521.A0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_143.CLK to */SLICE_143.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_143.Q1 to */SLICE_534.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]
CTOF_DEL    ---     0.260 */SLICE_534.A0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_320.CLK to */SLICE_320.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_320.Q0 to */SLICE_443.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[9]
CTOF_DEL    ---     0.260 */SLICE_443.C1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_319.CLK to */SLICE_319.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_319.Q0 to */SLICE_442.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[7]
CTOF_DEL    ---     0.260 */SLICE_442.C0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_156.CLK to */SLICE_156.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_156.Q0 to */SLICE_499.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]
CTOF_DEL    ---     0.260 */SLICE_499.A0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_155.CLK to */SLICE_155.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_155.Q1 to */SLICE_500.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]
CTOF_DEL    ---     0.260 */SLICE_500.A0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_155.CLK to */SLICE_155.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_155.Q0 to */SLICE_501.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]
CTOF_DEL    ---     0.260 */SLICE_501.A0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_130.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_130.A0 to */SLICE_130.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_264.CLK to */SLICE_264.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_264.Q0 to */SLICE_502.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[34]
CTOF_DEL    ---     0.260 */SLICE_502.C0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_263.CLK to */SLICE_263.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_263.Q1 to */SLICE_503.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[33]
CTOF_DEL    ---     0.260 */SLICE_503.C0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_263.CLK to */SLICE_263.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_263.Q0 to */SLICE_504.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[32]
CTOF_DEL    ---     0.260 */SLICE_504.C0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_262.CLK to */SLICE_262.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_262.Q1 to */SLICE_505.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[31]
CTOF_DEL    ---     0.260 */SLICE_505.C0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_262.CLK to */SLICE_262.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_262.Q0 to */SLICE_506.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[30]
CTOF_DEL    ---     0.260 */SLICE_506.C0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_261.CLK to */SLICE_261.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_261.Q1 to */SLICE_507.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[29]
CTOF_DEL    ---     0.260 */SLICE_507.C0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_261.CLK to */SLICE_261.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_261.Q0 to */SLICE_508.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[28]
CTOF_DEL    ---     0.260 */SLICE_508.C0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_260.CLK to */SLICE_260.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_260.Q1 to */SLICE_509.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[27]
CTOF_DEL    ---     0.260 */SLICE_509.C0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_260.CLK to */SLICE_260.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_260.Q0 to */SLICE_510.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[26]
CTOF_DEL    ---     0.260 */SLICE_510.C0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_259.CLK to */SLICE_259.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_259.Q1 to */SLICE_511.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[25]
CTOF_DEL    ---     0.260 */SLICE_511.C0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_259.CLK to */SLICE_259.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_259.Q0 to */SLICE_512.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[24]
CTOF_DEL    ---     0.260 */SLICE_512.C0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_258.CLK to */SLICE_258.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_258.Q1 to */SLICE_513.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[23]
CTOF_DEL    ---     0.260 */SLICE_513.C0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_167.CLK to */SLICE_167.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_167.Q1 to */SLICE_550.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.260 */SLICE_550.B0 to */SLICE_550.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 1.081 */SLICE_550.F0 to */SLICE_162.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_0[0]
CTOF_DEL    ---     0.260 */SLICE_162.B0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_257.CLK to */SLICE_257.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_257.Q1 to */SLICE_515.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[21]
CTOF_DEL    ---     0.260 */SLICE_515.C0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_164.CLK to */SLICE_164.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_164.Q0 to */SLICE_384.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.260 */SLICE_384.B0 to */SLICE_384.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_384
ROUTE         1   e 1.081 */SLICE_384.F0 to */SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.260 */SLICE_316.B1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_139.CLK to */SLICE_139.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_139.Q0 to */SLICE_524.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]
CTOF_DEL    ---     0.260 */SLICE_524.A0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_158.CLK to */SLICE_158.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_158.Q0 to */SLICE_495.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]
CTOF_DEL    ---     0.260 */SLICE_495.A0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_317.CLK to */SLICE_317.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_317.Q0 to */SLICE_383.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[4]
CTOF_DEL    ---     0.260 */SLICE_383.D0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_157.CLK to */SLICE_157.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_157.Q1 to */SLICE_496.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]
CTOF_DEL    ---     0.260 */SLICE_496.A0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_124.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_124.A0 to */SLICE_124.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_165.CLK to */SLICE_165.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_165.Q0 to */SLICE_386.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]
CTOF_DEL    ---     0.260 */SLICE_386.C0 to */SLICE_386.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_386
ROUTE         1   e 1.081 */SLICE_386.F0 to */SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.260 */SLICE_317.B1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_139.CLK to */SLICE_139.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_139.Q1 to */SLICE_528.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]
CTOF_DEL    ---     0.260 */SLICE_528.A0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_163.CLK to */SLICE_163.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_163.Q0 to */SLICE_380.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]
CTOF_DEL    ---     0.260 */SLICE_380.B0 to */SLICE_380.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_380
ROUTE         1   e 1.081 */SLICE_380.F0 to */SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.260 */SLICE_315.B1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_315.CLK to */SLICE_315.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE         8   e 1.081 */SLICE_315.Q1 to */SLICE_444.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[1]
CTOF_DEL    ---     0.260 */SLICE_444.C1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_138.CLK to */SLICE_138.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_138.Q0 to */SLICE_527.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]
CTOF_DEL    ---     0.260 */SLICE_527.A0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_137.CLK to */SLICE_137.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_137.Q1 to */SLICE_526.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]
CTOF_DEL    ---     0.260 */SLICE_526.A0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_162.CLK to */SLICE_162.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_162.Q1 to */SLICE_379.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]
CTOF_DEL    ---     0.260 */SLICE_379.B0 to */SLICE_379.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_379
ROUTE         1   e 1.081 */SLICE_379.F0 to */SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.260 */SLICE_315.B0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_171.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_171.B1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_397.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_397.B1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 1.081 */SLICE_397.F1 to */SLICE_112.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_112.D0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.001 */SLICE_112.F0 to *SLICE_112.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_257.CLK to */SLICE_257.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_257.Q0 to */SLICE_516.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[20]
CTOF_DEL    ---     0.260 */SLICE_516.C0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_256.CLK to */SLICE_256.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_256.Q1 to */SLICE_517.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[19]
CTOF_DEL    ---     0.260 */SLICE_517.C0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_256.CLK to */SLICE_256.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_256.Q0 to */SLICE_518.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[18]
CTOF_DEL    ---     0.260 */SLICE_518.C0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_255.CLK to */SLICE_255.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_255.Q1 to */SLICE_393.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[17]
CTOF_DEL    ---     0.260 */SLICE_393.C0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_255.CLK to */SLICE_255.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_255.Q0 to */SLICE_519.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[16]
CTOF_DEL    ---     0.260 */SLICE_519.C0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_254.CLK to */SLICE_254.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_254.Q1 to */SLICE_535.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[15]
CTOF_DEL    ---     0.260 */SLICE_535.C0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_322.CLK to */SLICE_322.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_322.Q1 to */SLICE_463.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[14]
CTOF_DEL    ---     0.260 */SLICE_463.C0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_254.CLK to */SLICE_254.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_254.Q0 to */SLICE_520.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[14]
CTOF_DEL    ---     0.260 */SLICE_520.C0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_322.CLK to */SLICE_322.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_322.Q0 to */SLICE_463.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[12]
CTOF_DEL    ---     0.260 */SLICE_463.C1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_252.CLK to */SLICE_252.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_252.Q1 to */SLICE_522.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[11]
CTOF_DEL    ---     0.260 */SLICE_522.C0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_445.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_445.D0 to */SLICE_445.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_445
ROUTE        16   e 1.081 */SLICE_445.F0 to */SLICE_321.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_55
MTOOFX_DEL  ---     0.260 */SLICE_321.M0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_320.CLK to */SLICE_320.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_320.Q1 to */SLICE_443.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[10]
CTOF_DEL    ---     0.260 */SLICE_443.C0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_252.CLK to */SLICE_252.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_252.Q0 to */SLICE_523.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[10]
CTOF_DEL    ---     0.260 */SLICE_523.C0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_167.CLK to */SLICE_167.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_167.Q0 to */SLICE_388.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]
CTOF_DEL    ---     0.260 */SLICE_388.C0 to */SLICE_388.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_388
ROUTE         1   e 1.081 */SLICE_388.F0 to */SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.260 */SLICE_320.B0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_319.CLK to */SLICE_319.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_319.Q1 to */SLICE_442.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[8]
CTOF_DEL    ---     0.260 */SLICE_442.C1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_251.CLK to */SLICE_251.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_251.Q0 to */SLICE_532.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[8]
CTOF_DEL    ---     0.260 */SLICE_532.C0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_166.CLK to */SLICE_166.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_166.Q0 to */SLICE_387.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]
CTOF_DEL    ---     0.260 */SLICE_387.C0 to */SLICE_387.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_387
ROUTE         1   e 1.081 */SLICE_387.F0 to */SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.260 */SLICE_319.B0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_142.CLK to */SLICE_142.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_142.Q0 to */SLICE_533.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]
CTOF_DEL    ---     0.260 */SLICE_533.A0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_141.CLK to */SLICE_141.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_141.Q0 to */SLICE_531.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]
CTOF_DEL    ---     0.260 */SLICE_531.A0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_140.CLK to */SLICE_140.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_140.Q1 to */SLICE_530.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]
CTOF_DEL    ---     0.260 */SLICE_530.A0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_543.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[0]
CTOF_DEL    ---     0.260 */SLICE_543.A0 to */SLICE_543.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 1.081 */SLICE_543.F0 to */SLICE_161.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_2
CTOF_DEL    ---     0.260 */SLICE_161.C0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_161.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_161.A0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_161.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_161.A0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B1 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_181.CLK to */SLICE_181.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_181.Q1 to */SLICE_542.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]
CTOF_DEL    ---     0.260 */SLICE_542.B0 to */SLICE_542.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 1.081 */SLICE_542.F0 to */SLICE_174.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_2_0[0]
CTOF_DEL    ---     0.260 */SLICE_174.D0 to */SLICE_174.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F0 to *SLICE_174.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_445.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_445.D0 to */SLICE_445.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_445
ROUTE        16   e 1.081 */SLICE_445.F0 to */SLICE_182.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.260 */SLICE_182.A0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_215.CLK to */SLICE_215.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_215.Q0 to *u/SLICE_35.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]
CTOF_DEL    ---     0.260 *u/SLICE_35.A1 to *u/SLICE_35.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F1 to */SLICE_215.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.260 */SLICE_215.D0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q1 to *u/SLICE_35.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]
CTOF_DEL    ---     0.260 *u/SLICE_35.A0 to *u/SLICE_35.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_35
ROUTE         1   e 1.081 *u/SLICE_35.F0 to */SLICE_214.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.260 */SLICE_214.D1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q0 to *u/SLICE_36.A1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
CTOF_DEL    ---     0.260 *u/SLICE_36.A1 to *u/SLICE_36.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 1.081 *u/SLICE_36.F1 to */SLICE_214.D0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.260 */SLICE_214.D0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay mg5ahub/SLICE_72 to mg5ahub/SLICE_72 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_72.CLK to *b/SLICE_72.Q0 mg5ahub/SLICE_72 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *b/SLICE_72.Q0 to */SLICE_453.C1 mg5ahub/bit_count_2
CTOF_DEL    ---     0.260 */SLICE_453.C1 to */SLICE_453.F1 mg5ahub/SLICE_453
ROUTE         1   e 1.081 */SLICE_453.F1 to *b/SLICE_72.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.260 *b/SLICE_72.C1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_72 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q0 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         6   e 1.081 *b/SLICE_71.Q0 to */SLICE_453.A1 mg5ahub/bit_count_0
CTOF_DEL    ---     0.260 */SLICE_453.A1 to */SLICE_453.F1 mg5ahub/SLICE_453
ROUTE         1   e 1.081 */SLICE_453.F1 to *b/SLICE_72.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.260 *b/SLICE_72.C1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_249.CLK to */SLICE_249.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_249.Q1 to */SLICE_529.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[5]
CTOF_DEL    ---     0.260 */SLICE_529.C0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_318.CLK to */SLICE_318.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_318.Q0 to */SLICE_382.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[6]
CTOF_DEL    ---     0.260 */SLICE_382.D0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_317.CLK to */SLICE_317.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_317.Q1 to */SLICE_462.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[5]
CTOF_DEL    ---     0.260 */SLICE_462.D0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_316.CLK to */SLICE_316.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_316.Q1 to */SLICE_444.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[3]
CTOF_DEL    ---     0.260 */SLICE_444.D0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *u/SLICE_36.A0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
CTOF_DEL    ---     0.260 *u/SLICE_36.A0 to *u/SLICE_36.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_36
ROUTE         1   e 1.081 *u/SLICE_36.F0 to */SLICE_213.D1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1]
CTOF_DEL    ---     0.260 */SLICE_213.D1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_248.CLK to */SLICE_248.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_248.Q0 to */SLICE_525.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[2]
CTOF_DEL    ---     0.260 */SLICE_525.C0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_258.CLK to */SLICE_258.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_258.Q0 to */SLICE_514.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[22]
CTOF_DEL    ---     0.260 */SLICE_514.C0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_159.CLK to */SLICE_159.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_159.Q1 to */SLICE_492.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]
CTOF_DEL    ---     0.260 */SLICE_492.A0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_171.CLK to */SLICE_171.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_171.Q0 to *u/SLICE_30.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.260 *u/SLICE_30.A1 to *u/SLICE_30.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_30
ROUTE         1   e 1.081 *u/SLICE_30.F1 to */SLICE_171.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0]
CTOF_DEL    ---     0.260 */SLICE_171.D0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_268.CLK to */SLICE_268.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_268.Q1 to */SLICE_493.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[43]
CTOF_DEL    ---     0.260 */SLICE_493.C0 to */SLICE_493.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_493
ROUTE         1   e 1.081 */SLICE_493.F0 to */SLICE_158.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1031
CTOF_DEL    ---     0.260 */SLICE_158.A1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_148.CLK to */SLICE_148.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_148.Q1 to */SLICE_514.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]
CTOF_DEL    ---     0.260 */SLICE_514.A0 to */SLICE_514.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_514
ROUTE         1   e 1.081 */SLICE_514.F0 to */SLICE_148.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_695
CTOF_DEL    ---     0.260 */SLICE_148.A0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_148.CLK to */SLICE_148.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_148.Q0 to */SLICE_515.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]
CTOF_DEL    ---     0.260 */SLICE_515.A0 to */SLICE_515.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_515
ROUTE         1   e 1.081 */SLICE_515.F0 to */SLICE_147.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_679
CTOF_DEL    ---     0.260 */SLICE_147.A1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_147.CLK to */SLICE_147.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_147.Q1 to */SLICE_516.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]
CTOF_DEL    ---     0.260 */SLICE_516.A0 to */SLICE_516.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_516
ROUTE         1   e 1.081 */SLICE_516.F0 to */SLICE_147.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_663
CTOF_DEL    ---     0.260 */SLICE_147.A0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_147.CLK to */SLICE_147.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_147.Q0 to */SLICE_517.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]
CTOF_DEL    ---     0.260 */SLICE_517.A0 to */SLICE_517.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_517
ROUTE         1   e 1.081 */SLICE_517.F0 to */SLICE_146.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_647
CTOF_DEL    ---     0.260 */SLICE_146.A1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_146.CLK to */SLICE_146.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_146.Q1 to */SLICE_518.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]
CTOF_DEL    ---     0.260 */SLICE_518.A0 to */SLICE_518.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_518
ROUTE         1   e 1.081 */SLICE_518.F0 to */SLICE_146.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_631
CTOF_DEL    ---     0.260 */SLICE_146.A0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_146.CLK to */SLICE_146.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_146.Q0 to */SLICE_393.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]
CTOF_DEL    ---     0.260 */SLICE_393.A0 to */SLICE_393.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE         1   e 1.081 */SLICE_393.F0 to */SLICE_145.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_615
CTOF_DEL    ---     0.260 */SLICE_145.A1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_145.CLK to */SLICE_145.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_145.Q1 to */SLICE_519.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]
CTOF_DEL    ---     0.260 */SLICE_519.A0 to */SLICE_519.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_519
ROUTE         1   e 1.081 */SLICE_519.F0 to */SLICE_145.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_599
CTOF_DEL    ---     0.260 */SLICE_145.A0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_145.CLK to */SLICE_145.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_145.Q0 to */SLICE_535.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]
CTOF_DEL    ---     0.260 */SLICE_535.A0 to */SLICE_535.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_535
ROUTE         1   e 1.081 */SLICE_535.F0 to */SLICE_144.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_583
CTOF_DEL    ---     0.260 */SLICE_144.A1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_169.CLK to */SLICE_169.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_169.Q1 to */SLICE_391.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]
CTOF_DEL    ---     0.260 */SLICE_391.C0 to */SLICE_391.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_391
ROUTE         1   e 1.081 */SLICE_391.F0 to */SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.260 */SLICE_322.B1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_144.CLK to */SLICE_144.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_144.Q1 to */SLICE_520.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]
CTOF_DEL    ---     0.260 */SLICE_520.A0 to */SLICE_520.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_520
ROUTE         1   e 1.081 */SLICE_520.F0 to */SLICE_144.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_567
CTOF_DEL    ---     0.260 */SLICE_144.A0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_253.CLK to */SLICE_253.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_253.Q1 to */SLICE_521.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[13]
CTOF_DEL    ---     0.260 */SLICE_521.C0 to */SLICE_521.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_521
ROUTE         1   e 1.081 */SLICE_521.F0 to */SLICE_143.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_551
CTOF_DEL    ---     0.260 */SLICE_143.A1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_167.CLK to */SLICE_167.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_167.Q1 to */SLICE_389.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.260 */SLICE_389.C0 to */SLICE_389.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_389
ROUTE         1   e 1.081 */SLICE_389.F0 to */SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.260 */SLICE_320.B1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_142.CLK to */SLICE_142.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_142.Q1 to */SLICE_523.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]
CTOF_DEL    ---     0.260 */SLICE_523.A0 to */SLICE_523.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_523
ROUTE         1   e 1.081 */SLICE_523.F0 to */SLICE_142.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_503
CTOF_DEL    ---     0.260 */SLICE_142.A0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_166.CLK to */SLICE_166.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_166.Q1 to */SLICE_490.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]
CTOF_DEL    ---     0.260 */SLICE_490.B0 to */SLICE_490.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_490
ROUTE         1   e 1.081 */SLICE_490.F0 to */SLICE_319.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.260 */SLICE_319.B1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_141.CLK to */SLICE_141.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_141.Q1 to */SLICE_532.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]
CTOF_DEL    ---     0.260 */SLICE_532.A0 to */SLICE_532.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_532
ROUTE         1   e 1.081 */SLICE_532.F0 to */SLICE_141.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_471
CTOF_DEL    ---     0.260 */SLICE_141.A0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_168.CLK to */SLICE_168.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_168.Q1 to */SLICE_390.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]
CTOF_DEL    ---     0.260 */SLICE_390.C0 to */SLICE_390.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_390
ROUTE         1   e 1.081 */SLICE_390.F0 to */SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.260 */SLICE_322.B0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_143.CLK to */SLICE_143.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_143.Q0 to */SLICE_522.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]
CTOF_DEL    ---     0.260 */SLICE_522.A0 to */SLICE_522.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_522
ROUTE         1   e 1.081 */SLICE_522.F0 to */SLICE_142.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_519
CTOF_DEL    ---     0.260 */SLICE_142.A1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_317.CLK to */SLICE_317.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_317.Q1 to */SLICE_382.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[5]
CTOF_DEL    ---     0.260 */SLICE_382.C0 to */SLICE_382.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382
ROUTE         1   e 1.081 */SLICE_382.F0 to */SLICE_317.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.260 */SLICE_317.C1 to */SLICE_317.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F1 to *SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_249.CLK to */SLICE_249.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_249.Q0 to */SLICE_528.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[4]
CTOF_DEL    ---     0.260 */SLICE_528.C0 to */SLICE_528.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_528
ROUTE         1   e 1.081 */SLICE_528.F0 to */SLICE_139.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_407
CTOF_DEL    ---     0.260 */SLICE_139.A0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_164.CLK to */SLICE_164.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_164.Q1 to */SLICE_385.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]
CTOF_DEL    ---     0.260 */SLICE_385.C0 to */SLICE_385.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_385
ROUTE         1   e 1.081 */SLICE_385.F0 to */SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.260 */SLICE_317.B0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_316.CLK to */SLICE_316.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_316.Q1 to */SLICE_383.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[3]
CTOF_DEL    ---     0.260 */SLICE_383.C0 to */SLICE_383.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_383
ROUTE         1   e 1.081 */SLICE_383.F0 to */SLICE_316.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.260 */SLICE_316.C1 to */SLICE_316.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F1 to *SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_248.CLK to */SLICE_248.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_248.Q1 to */SLICE_524.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[3]
CTOF_DEL    ---     0.260 */SLICE_524.C0 to */SLICE_524.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_524
ROUTE         1   e 1.081 */SLICE_524.F0 to */SLICE_138.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_391
CTOF_DEL    ---     0.260 */SLICE_138.A1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_163.CLK to */SLICE_163.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_163.Q1 to */SLICE_381.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]
CTOF_DEL    ---     0.260 */SLICE_381.B0 to */SLICE_381.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_381
ROUTE         1   e 1.081 */SLICE_381.F0 to */SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.260 */SLICE_316.B0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_138.CLK to */SLICE_138.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_138.Q1 to */SLICE_525.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]
CTOF_DEL    ---     0.260 */SLICE_525.A0 to */SLICE_525.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_525
ROUTE         1   e 1.081 */SLICE_525.F0 to */SLICE_138.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_375
CTOF_DEL    ---     0.260 */SLICE_138.A0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_316.CLK to */SLICE_316.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (from jtaghub16_jtck)
ROUTE         8   e 1.081 */SLICE_316.Q0 to */SLICE_444.D1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[2]
CTOF_DEL    ---     0.260 */SLICE_444.D1 to */SLICE_444.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F1 to */SLICE_315.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.260 */SLICE_315.C1 to */SLICE_315.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F1 to *SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_392.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_392.B1 to */SLICE_392.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         2   e 1.081 */SLICE_392.F1 to */SLICE_174.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1118
CTOF_DEL    ---     0.260 */SLICE_174.A0 to */SLICE_174.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F0 to *SLICE_174.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_445.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_445.C0 to */SLICE_445.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_445
ROUTE        16   e 1.081 */SLICE_445.F0 to */SLICE_182.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.260 */SLICE_182.A0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_215.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_215.A0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_214.A1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_214.A1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_214.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_214.A0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_268.CLK to */SLICE_268.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_268.Q0 to */SLICE_494.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[42]
CTOF_DEL    ---     0.260 */SLICE_494.C0 to */SLICE_494.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_494
ROUTE         1   e 1.081 */SLICE_494.F0 to */SLICE_158.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1015
CTOF_DEL    ---     0.260 */SLICE_158.A0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_149.CLK to */SLICE_149.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_149.Q0 to */SLICE_513.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]
CTOF_DEL    ---     0.260 */SLICE_513.A0 to */SLICE_513.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_513
ROUTE         1   e 1.081 */SLICE_513.F0 to */SLICE_148.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_711
CTOF_DEL    ---     0.260 */SLICE_148.A1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_315.CLK to */SLICE_315.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE        22   e 1.081 */SLICE_315.Q0 to */SLICE_462.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[0]
CTOF_DEL    ---     0.260 */SLICE_462.C1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_161.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_161.A0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_164.CLK to */SLICE_164.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_164.Q0 to */SLICE_550.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.260 */SLICE_550.A0 to */SLICE_550.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 1.081 */SLICE_550.F0 to */SLICE_162.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_0[0]
CTOF_DEL    ---     0.260 */SLICE_162.B0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_172.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_172.B0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_213.A1 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_213.A1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay mg5ahub/SLICE_73 to mg5ahub/SLICE_72 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_73.CLK to *b/SLICE_73.Q0 mg5ahub/SLICE_73 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *b/SLICE_73.Q0 to */SLICE_453.D1 mg5ahub/bit_count_3
CTOF_DEL    ---     0.260 */SLICE_453.D1 to */SLICE_453.F1 mg5ahub/SLICE_453
ROUTE         1   e 1.081 */SLICE_453.F1 to *b/SLICE_72.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.260 *b/SLICE_72.C1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_267.CLK to */SLICE_267.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_267.Q1 to */SLICE_495.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[41]
CTOF_DEL    ---     0.260 */SLICE_495.C0 to */SLICE_495.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_495
ROUTE         1   e 1.081 */SLICE_495.F0 to */SLICE_157.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_999
CTOF_DEL    ---     0.260 */SLICE_157.A1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_266.CLK to */SLICE_266.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_266.Q1 to */SLICE_497.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[39]
CTOF_DEL    ---     0.260 */SLICE_497.C0 to */SLICE_497.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_497
ROUTE         1   e 1.081 */SLICE_497.F0 to */SLICE_156.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_967
CTOF_DEL    ---     0.260 */SLICE_156.A1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_315.CLK to */SLICE_315.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE         8   e 1.081 */SLICE_315.Q1 to */SLICE_462.D1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[1]
CTOF_DEL    ---     0.260 */SLICE_462.D1 to */SLICE_462.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F1 to */SLICE_315.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.260 */SLICE_315.C0 to */SLICE_315.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315
ROUTE         1   e 0.001 */SLICE_315.F0 to *SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_154.CLK to */SLICE_154.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_154.Q1 to */SLICE_502.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]
CTOF_DEL    ---     0.260 */SLICE_502.A0 to */SLICE_502.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_502
ROUTE         1   e 1.081 */SLICE_502.F0 to */SLICE_154.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_887
CTOF_DEL    ---     0.260 */SLICE_154.A0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_153.CLK to */SLICE_153.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_153.Q1 to */SLICE_504.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]
CTOF_DEL    ---     0.260 */SLICE_504.A0 to */SLICE_504.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_504
ROUTE         1   e 1.081 */SLICE_504.F0 to */SLICE_153.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_855
CTOF_DEL    ---     0.260 */SLICE_153.A0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_152.CLK to */SLICE_152.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_152.Q1 to */SLICE_506.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]
CTOF_DEL    ---     0.260 */SLICE_506.A0 to */SLICE_506.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_506
ROUTE         1   e 1.081 */SLICE_506.F0 to */SLICE_152.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_823
CTOF_DEL    ---     0.260 */SLICE_152.A0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_150.CLK to */SLICE_150.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_150.Q0 to */SLICE_511.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]
CTOF_DEL    ---     0.260 */SLICE_511.A0 to */SLICE_511.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_511
ROUTE         1   e 1.081 */SLICE_511.F0 to */SLICE_149.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_743
CTOF_DEL    ---     0.260 */SLICE_149.A1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_264.CLK to */SLICE_264.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_264.Q1 to */SLICE_501.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[35]
CTOF_DEL    ---     0.260 */SLICE_501.C0 to */SLICE_501.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_501
ROUTE         1   e 1.081 */SLICE_501.F0 to */SLICE_154.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_903
CTOF_DEL    ---     0.260 */SLICE_154.A1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_253.CLK to */SLICE_253.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_253.Q0 to */SLICE_534.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[12]
CTOF_DEL    ---     0.260 */SLICE_534.C0 to */SLICE_534.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_534
ROUTE         1   e 1.081 */SLICE_534.F0 to */SLICE_143.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_535
CTOF_DEL    ---     0.260 */SLICE_143.A0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_321.CLK to */SLICE_321.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_321.Q0 to */SLICE_443.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[11]
CTOF_DEL    ---     0.260 */SLICE_443.D0 to */SLICE_443.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F0 to */SLICE_320.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.260 */SLICE_320.C1 to */SLICE_320.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F1 to *SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_320.CLK to */SLICE_320.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_320.Q0 to */SLICE_442.D1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[9]
CTOF_DEL    ---     0.260 */SLICE_442.D1 to */SLICE_442.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F1 to */SLICE_319.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.260 */SLICE_319.C1 to */SLICE_319.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F1 to *SLICE_319.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_251.CLK to */SLICE_251.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_251.Q1 to */SLICE_533.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[9]
CTOF_DEL    ---     0.260 */SLICE_533.C0 to */SLICE_533.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_533
ROUTE         1   e 1.081 */SLICE_533.F0 to */SLICE_141.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_487
CTOF_DEL    ---     0.260 */SLICE_141.A1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_149.CLK to */SLICE_149.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_149.Q1 to */SLICE_512.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]
CTOF_DEL    ---     0.260 */SLICE_512.A0 to */SLICE_512.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_512
ROUTE         1   e 1.081 */SLICE_512.F0 to */SLICE_149.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_727
CTOF_DEL    ---     0.260 */SLICE_149.A0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_397.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_397.A1 to */SLICE_397.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_397
ROUTE         2   e 1.081 */SLICE_397.F1 to */SLICE_112.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un2_jupdate_int
CTOF_DEL    ---     0.260 */SLICE_112.D0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.001 */SLICE_112.F0 to *SLICE_112.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_124.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_124.C0 to */SLICE_124.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_395.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_395.B1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_124.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_124.A0 to */SLICE_124.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 1.081 */SLICE_118.F0 to */SLICE_184.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int
CTOF_DEL    ---     0.260 */SLICE_184.B0 to */SLICE_184.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184
ROUTE         1   e 0.001 */SLICE_184.F0 to *SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_160.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_160.B0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_269.CLK to */SLICE_269.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_269.Q1 to */SLICE_491.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[45]
CTOF_DEL    ---     0.260 */SLICE_491.C0 to */SLICE_491.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_491
ROUTE         1   e 1.081 */SLICE_491.F0 to */SLICE_159.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1063
CTOF_DEL    ---     0.260 */SLICE_159.A1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_269.CLK to */SLICE_269.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_269.Q0 to */SLICE_492.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[44]
CTOF_DEL    ---     0.260 */SLICE_492.C0 to */SLICE_492.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_492
ROUTE         1   e 1.081 */SLICE_492.F0 to */SLICE_159.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1047
CTOF_DEL    ---     0.260 */SLICE_159.A0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_247.CLK to */SLICE_247.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_247.Q1 to */SLICE_527.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[1]
CTOF_DEL    ---     0.260 */SLICE_527.C0 to */SLICE_527.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_527
ROUTE         1   e 1.081 */SLICE_527.F0 to */SLICE_137.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_359
CTOF_DEL    ---     0.260 */SLICE_137.A1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_247.CLK to */SLICE_247.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_247.Q0 to */SLICE_526.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.260 */SLICE_526.C0 to */SLICE_526.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_526
ROUTE         1   e 1.081 */SLICE_526.F0 to */SLICE_137.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_343
CTOF_DEL    ---     0.260 */SLICE_137.A0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_408.CLK to */SLICE_408.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (from jtaghub16_jtck)
ROUTE        10   e 1.081 */SLICE_408.Q0 to */SLICE_445.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.260 */SLICE_445.D0 to */SLICE_445.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_445
ROUTE        16   e 1.081 */SLICE_445.F0 to */SLICE_318.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_55
MTOOFX_DEL  ---     0.260 */SLICE_318.M0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_543.B0 top_reveal_coretop_instance/top_la0_inst_0/addr[1]
CTOF_DEL    ---     0.260 */SLICE_543.B0 to */SLICE_543.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 1.081 */SLICE_543.F0 to */SLICE_161.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_2
CTOF_DEL    ---     0.260 */SLICE_161.C0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_140.CLK to */SLICE_140.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_140.Q0 to */SLICE_529.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]
CTOF_DEL    ---     0.260 */SLICE_529.A0 to */SLICE_529.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_529
ROUTE         1   e 1.081 */SLICE_529.F0 to */SLICE_139.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_423
CTOF_DEL    ---     0.260 */SLICE_139.A1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_169.CLK to */SLICE_169.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_169.Q1 to */SLICE_550.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]
CTOF_DEL    ---     0.260 */SLICE_550.C0 to */SLICE_550.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 1.081 */SLICE_550.F0 to */SLICE_162.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_RNO_0[0]
CTOF_DEL    ---     0.260 */SLICE_162.B0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_317.CLK to */SLICE_317.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_317.Q0 to */SLICE_462.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[4]
CTOF_DEL    ---     0.260 */SLICE_462.C0 to */SLICE_462.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_462
ROUTE         1   e 1.081 */SLICE_462.F0 to */SLICE_317.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.260 */SLICE_317.C0 to */SLICE_317.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317
ROUTE         1   e 0.001 */SLICE_317.F0 to *SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_173.CLK to */SLICE_173.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_173.Q1 to */SLICE_393.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.260 */SLICE_393.C1 to */SLICE_393.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_393
ROUTE        54   e 1.081 */SLICE_393.F1 to */SLICE_173.B0 top_reveal_coretop_instance/top_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.260 */SLICE_173.B0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_250.CLK to */SLICE_250.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_250.Q0 to */SLICE_530.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[6]
CTOF_DEL    ---     0.260 */SLICE_530.C0 to */SLICE_530.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_530
ROUTE         1   e 1.081 */SLICE_530.F0 to */SLICE_140.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_439
CTOF_DEL    ---     0.260 */SLICE_140.A0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_437.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_437.D0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_171.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.260 */SLICE_171.C1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_152.CLK to */SLICE_152.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_152.Q0 to */SLICE_507.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]
CTOF_DEL    ---     0.260 */SLICE_507.A0 to */SLICE_507.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_507
ROUTE         1   e 1.081 */SLICE_507.F0 to */SLICE_151.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_807
CTOF_DEL    ---     0.260 */SLICE_151.A1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_213.A0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_213.A0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_151.CLK to */SLICE_151.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_151.Q1 to */SLICE_508.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]
CTOF_DEL    ---     0.260 */SLICE_508.A0 to */SLICE_508.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_508
ROUTE         1   e 1.081 */SLICE_508.F0 to */SLICE_151.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_791
CTOF_DEL    ---     0.260 */SLICE_151.A0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_72 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q1 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         5   e 1.081 *b/SLICE_71.Q1 to */SLICE_453.B1 mg5ahub/bit_count_1
CTOF_DEL    ---     0.260 */SLICE_453.B1 to */SLICE_453.F1 mg5ahub/SLICE_453
ROUTE         1   e 1.081 */SLICE_453.F1 to *b/SLICE_72.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.260 *b/SLICE_72.C1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_151.CLK to */SLICE_151.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_151.Q0 to */SLICE_509.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]
CTOF_DEL    ---     0.260 */SLICE_509.A0 to */SLICE_509.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_509
ROUTE         1   e 1.081 */SLICE_509.F0 to */SLICE_150.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_775
CTOF_DEL    ---     0.260 */SLICE_150.A1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_267.CLK to */SLICE_267.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_267.Q0 to */SLICE_496.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[40]
CTOF_DEL    ---     0.260 */SLICE_496.C0 to */SLICE_496.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_496
ROUTE         1   e 1.081 */SLICE_496.F0 to */SLICE_157.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_983
CTOF_DEL    ---     0.260 */SLICE_157.A0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_150.CLK to */SLICE_150.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_150.Q1 to */SLICE_510.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]
CTOF_DEL    ---     0.260 */SLICE_510.A0 to */SLICE_510.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_510
ROUTE         1   e 1.081 */SLICE_510.F0 to */SLICE_150.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_759
CTOF_DEL    ---     0.260 */SLICE_150.A0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_316.CLK to */SLICE_316.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (from jtaghub16_jtck)
ROUTE         8   e 1.081 */SLICE_316.Q0 to */SLICE_444.C0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[2]
CTOF_DEL    ---     0.260 */SLICE_444.C0 to */SLICE_444.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_444
ROUTE         1   e 1.081 */SLICE_444.F0 to */SLICE_316.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.260 */SLICE_316.C0 to */SLICE_316.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316
ROUTE         1   e 0.001 */SLICE_316.F0 to *SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_395.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_395.A1 to */SLICE_395.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE         5   e 1.081 */SLICE_395.F1 to */SLICE_130.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1117
CTOF_DEL    ---     0.260 */SLICE_130.A0 to */SLICE_130.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_154.CLK to */SLICE_154.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_154.Q0 to */SLICE_503.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]
CTOF_DEL    ---     0.260 */SLICE_503.A0 to */SLICE_503.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_503
ROUTE         1   e 1.081 */SLICE_503.F0 to */SLICE_153.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_871
CTOF_DEL    ---     0.260 */SLICE_153.A1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_153.CLK to */SLICE_153.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_153.Q0 to */SLICE_505.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]
CTOF_DEL    ---     0.260 */SLICE_505.A0 to */SLICE_505.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505
ROUTE         1   e 1.081 */SLICE_505.F0 to */SLICE_152.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_839
CTOF_DEL    ---     0.260 */SLICE_152.A1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_266.CLK to */SLICE_266.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_266.Q0 to */SLICE_498.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[38]
CTOF_DEL    ---     0.260 */SLICE_498.C0 to */SLICE_498.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_498
ROUTE         1   e 1.081 */SLICE_498.F0 to */SLICE_156.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_951
CTOF_DEL    ---     0.260 */SLICE_156.A0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_265.CLK to */SLICE_265.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_265.Q0 to */SLICE_500.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[36]
CTOF_DEL    ---     0.260 */SLICE_500.C0 to */SLICE_500.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_500
ROUTE         1   e 1.081 */SLICE_500.F0 to */SLICE_155.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_919
CTOF_DEL    ---     0.260 */SLICE_155.A0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_130.B0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr
CTOF_DEL    ---     0.260 */SLICE_130.B0 to */SLICE_130.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_323.CLK to */SLICE_323.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_323.Q0 to */SLICE_463.D1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[13]
CTOF_DEL    ---     0.260 */SLICE_463.D1 to */SLICE_463.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F1 to */SLICE_322.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.260 */SLICE_322.C0 to */SLICE_322.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F0 to *SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_320.CLK to */SLICE_320.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_320.Q1 to */SLICE_443.D1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[10]
CTOF_DEL    ---     0.260 */SLICE_443.D1 to */SLICE_443.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_443
ROUTE         1   e 1.081 */SLICE_443.F1 to */SLICE_320.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.260 */SLICE_320.C0 to */SLICE_320.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320
ROUTE         1   e 0.001 */SLICE_320.F0 to *SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_319.CLK to */SLICE_319.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_319.Q1 to */SLICE_442.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[8]
CTOF_DEL    ---     0.260 */SLICE_442.D0 to */SLICE_442.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_442
ROUTE         1   e 1.081 */SLICE_442.F0 to */SLICE_319.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.260 */SLICE_319.C0 to */SLICE_319.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319
ROUTE         1   e 0.001 */SLICE_319.F0 to *SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_250.CLK to */SLICE_250.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_250.Q1 to */SLICE_531.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[7]
CTOF_DEL    ---     0.260 */SLICE_531.C0 to */SLICE_531.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_531
ROUTE         1   e 1.081 */SLICE_531.F0 to */SLICE_140.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_455
CTOF_DEL    ---     0.260 */SLICE_140.A1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.159ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (3.066ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_265.CLK to */SLICE_265.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_265.Q1 to */SLICE_499.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[37]
CTOF_DEL    ---     0.260 */SLICE_499.C0 to */SLICE_499.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_499
ROUTE         1   e 1.081 */SLICE_499.F0 to */SLICE_155.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_935
CTOF_DEL    ---     0.260 */SLICE_155.A1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    3.066   (29.5% logic, 70.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_156.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_145.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_177.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_135.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_147.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_181.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_31.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_541.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_541.A0 to */SLICE_541.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 1.081 */SLICE_541.F0 to */SLICE_109.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_151.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_140.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_190 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_190.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_143.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_160.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_153.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_97.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_118.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_118.A1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_424.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_539.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_539.A0 to */SLICE_539.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 1.081 */SLICE_539.F0 to */SLICE_548.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_345.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_100.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_127.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_179.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_456.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_118.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_118.A1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_408.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_98.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_138.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_175.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_133.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_157.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_150.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_176.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_141.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_405.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_95.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_463.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_152.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_148.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_137.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_437.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_437.A0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_378.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_154.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_180.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_33.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_134.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_118.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_118.A1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_410.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_34.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_146.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_144.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_158.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_149.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_178.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_128.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_392.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_392.C0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_174.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to *u/SLICE_32.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_96.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_159.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_142.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_136.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_99.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_139.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_344.C0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_395.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_395.B0 to */SLICE_395.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395
ROUTE        29   e 1.081 */SLICE_395.F0 to */SLICE_155.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_107.A1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_94.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_345.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.C1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_410.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_133.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_99.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_96.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_94.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_405.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_178.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_128.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_456.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_174.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_136.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_304.Q0 to */SLICE_367.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_367.D0 to */SLICE_367.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367
ROUTE         1   e 1.081 */SLICE_367.F0 to */SLICE_302.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.D1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_424.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.B1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_424.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_135.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_100.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_98.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_97.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_127.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_95.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_76 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_76.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_78 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_78.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_177.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_215.B1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_215.B1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_214.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_80 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_80.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_82 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_82.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_449.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_449.D1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.C1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_408.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_74 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_74.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_463.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_368.C0 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_368.C0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_378.C0 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_378.C0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_181.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_134.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_180.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_96.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.B1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_410.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_118.CLK to */SLICE_118.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_118.Q0 to */SLICE_539.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1
CTOF_DEL    ---     0.260 */SLICE_539.C0 to */SLICE_539.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 1.081 */SLICE_539.F0 to */SLICE_548.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.D1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_410.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_456.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_94.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_405.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_128.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_99.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_133.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_345.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_176.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_437.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_437.D0 to */SLICE_437.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437
ROUTE         3   e 1.081 */SLICE_437.F0 to */SLICE_378.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_136.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_285.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_75 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_75.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_77 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_77.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_79 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_79.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_81 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_81.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.C1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_424.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.D1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_408.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.B1 to */SLICE_118.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         3   e 1.081 */SLICE_118.F1 to */SLICE_408.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_135.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_284.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_304.Q0 to */SLICE_368.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_368.D0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_134.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_215.B1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_215.B1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 1.081 */SLICE_215.F1 to */SLICE_213.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_378.C0 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_378.C0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_100.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_369.A1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_369.A1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_179.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_83 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to */SLICE_569.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_569.B0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_83.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_290.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_98.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_127.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_95.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_107.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_107.C1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to */SLICE_463.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_183.Q0 to */SLICE_392.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_392.D0 to */SLICE_392.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392
ROUTE         8   e 1.081 */SLICE_392.F0 to */SLICE_175.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_289.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_288.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_287.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_212.Q1 to */SLICE_424.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.260 */SLICE_424.B0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_286.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_369.Q0 to */SLICE_449.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_449.C1 to */SLICE_449.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449
ROUTE         8   e 1.081 */SLICE_449.F1 to */SLICE_291.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_107.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_107.D1 to */SLICE_107.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        17   e 1.081 */SLICE_107.F1 to *u/SLICE_97.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61 (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.049ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (2.805ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_378.C0 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_378.C0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.953ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (2.805ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 1.081 */SLICE_107.F0 to */SLICE_369.M0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr (to jtaghub16_jtck)
                  --------
                    2.805   (22.9% logic, 77.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.824ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (2.731ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.790 *u/SLICE_34.B0 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_32.FCI to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    2.731   (60.3% logic, 39.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (2.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.790 *u/SLICE_34.B0 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.081 */SLICE_32.FCI to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    2.725   (60.2% logic, 39.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_112.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_112.A0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.280 */SLICE_112.F0 to */SLICE_112.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_112.B1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_112.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_112.B0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.280 */SLICE_112.F0 to */SLICE_112.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_112.B1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_257.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_265.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_251.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_267.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_249.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_247.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_269.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_259.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_255.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_263.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_261.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_253.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_112.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_112.C0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.280 */SLICE_112.F0 to */SLICE_112.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.260 */SLICE_112.B1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_268.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_256.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_254.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_258.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_264.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_248.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_270.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_266.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_252.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_262.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_250.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.788ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (2.544ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 0.280 */SLICE_424.F1 to */SLICE_424.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_424.C0 to */SLICE_424.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE        24   e 1.081 */SLICE_424.F0 to */SLICE_260.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.544   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.742ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (2.649ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.790 *u/SLICE_34.B0 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF1_DE  ---     0.393 */SLICE_33.FCI to *u/SLICE_33.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F1 to */SLICE_33.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    2.649   (59.1% logic, 40.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.736ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (2.643ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.790 *u/SLICE_34.B0 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_32.FCI to *u/SLICE_32.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F0 to */SLICE_32.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    2.643   (59.0% logic, 41.0% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.654ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (2.561ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.790 *u/SLICE_34.B0 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF0_DE  ---     0.305 */SLICE_33.FCI to *u/SLICE_33.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F0 to */SLICE_33.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    2.561   (57.7% logic, 42.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_161.A1 top_reveal_coretop_instance/top_la0_inst_0/addr[2]
CTOF_DEL    ---     0.260 */SLICE_161.A1 to */SLICE_161.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.280 */SLICE_161.F1 to */SLICE_161.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_3
CTOF_DEL    ---     0.260 */SLICE_161.D0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_302.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_302.A1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 0.280 */SLICE_302.F1 to */SLICE_302.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_302.A0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_314.Q0 to */SLICE_183.D1 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_183.D1 to */SLICE_183.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.280 */SLICE_183.F1 to */SLICE_183.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_0_1
CTOF_DEL    ---     0.260 */SLICE_183.D0 to */SLICE_183.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.001 */SLICE_183.F0 to *SLICE_183.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_463.CLK to */SLICE_463.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_463.Q0 to */SLICE_463.D0 top_reveal_coretop_instance/top_la0_inst_0/wr_din[15]
CTOF_DEL    ---     0.260 */SLICE_463.D0 to */SLICE_463.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463
ROUTE         1   e 1.081 */SLICE_463.F0 to */SLICE_322.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.260 */SLICE_322.C1 to */SLICE_322.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322
ROUTE         1   e 0.001 */SLICE_322.F1 to *SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_161.D1 top_reveal_coretop_instance/top_la0_inst_0/addr[13]
CTOF_DEL    ---     0.260 */SLICE_161.D1 to */SLICE_161.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.280 */SLICE_161.F1 to */SLICE_161.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_3
CTOF_DEL    ---     0.260 */SLICE_161.D0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q0 to */SLICE_182.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.260 */SLICE_182.D1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_211.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.260 */SLICE_211.C1 to */SLICE_211.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.280 */SLICE_211.F1 to */SLICE_211.B0 top_reveal_coretop_instance/top_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.260 */SLICE_211.B0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_286.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_286.A1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_285.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_285.A1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_284.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_284.A1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_291.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_291.A1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_290.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_290.A1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_289.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_289.A1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_302.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_302.B1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 0.280 */SLICE_302.F1 to */SLICE_302.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_302.A0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_304.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_304.A0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to */SLICE_161.C1 top_reveal_coretop_instance/top_la0_inst_0/addr[12]
CTOF_DEL    ---     0.260 */SLICE_161.C1 to */SLICE_161.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.280 */SLICE_161.F1 to */SLICE_161.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_3
CTOF_DEL    ---     0.260 */SLICE_161.D0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_135.CLK to */SLICE_135.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_135.Q1 to */SLICE_182.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.260 */SLICE_182.C1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_183.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_183.C1 to */SLICE_183.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.280 */SLICE_183.F1 to */SLICE_183.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_0_1
CTOF_DEL    ---     0.260 */SLICE_183.D0 to */SLICE_183.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.001 */SLICE_183.F0 to *SLICE_183.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_288.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_288.A1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_161.B1 top_reveal_coretop_instance/top_la0_inst_0/addr[4]
CTOF_DEL    ---     0.260 */SLICE_161.B1 to */SLICE_161.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.280 */SLICE_161.F1 to */SLICE_161.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_r_w4_3
CTOF_DEL    ---     0.260 */SLICE_161.D0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 1.081 */SLICE_113.Q0 to */SLICE_183.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.260 */SLICE_183.B1 to */SLICE_183.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.280 */SLICE_183.F1 to */SLICE_183.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_0_1
CTOF_DEL    ---     0.260 */SLICE_183.D0 to */SLICE_183.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.001 */SLICE_183.F0 to *SLICE_183.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 1.081 */SLICE_302.F1 to */SLICE_287.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_287.A1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_214.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_214.C0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_213.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_213.C0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.358ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (2.265ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 0.280 */SLICE_424.Q0 to */SLICE_424.A1 top_reveal_coretop_instance/top_la0_inst_0/addr_15
CTOF_DEL    ---     0.260 */SLICE_424.A1 to */SLICE_424.F1 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424
ROUTE         7   e 1.081 */SLICE_424.F1 to */SLICE_215.C0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.260 */SLICE_215.C0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    2.265   (39.9% logic, 60.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_83 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_83.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_168.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_162.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_378.CLK to */SLICE_378.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_378.Q0 to */SLICE_378.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.260 */SLICE_378.D0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_172.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_215.B1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_215.B1 to */SLICE_215.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         3   e 0.280 */SLICE_215.F1 to */SLICE_215.CE top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_539.CLK to */SLICE_539.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_539.Q0 to */SLICE_539.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3
CTOF_DEL    ---     0.260 */SLICE_539.B0 to */SLICE_539.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 1.081 */SLICE_539.F0 to */SLICE_548.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_368.Q0 to */SLICE_368.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_368.B0 to */SLICE_368.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368
ROUTE         1   e 1.081 */SLICE_368.F0 to */SLICE_314.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_79 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_79.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_166.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_164.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_81 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_81.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_75 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_75.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_77 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_77.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_122.CLK to */SLICE_122.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c)
ROUTE         5   e 1.081 */SLICE_122.Q0 to */SLICE_112.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.260 */SLICE_112.C1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_163.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_76 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_76.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_167.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_369.CLK to */SLICE_369.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_369.Q0 to */SLICE_369.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.260 */SLICE_369.B1 to */SLICE_369.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369
ROUTE         1   e 1.081 */SLICE_369.F1 to */SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_378.CLK to */SLICE_378.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_378.Q0 to */SLICE_378.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.260 */SLICE_378.D0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_173.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_74 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_74.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_378.CLK to */SLICE_378.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_378.Q0 to */SLICE_378.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.260 */SLICE_378.D0 to */SLICE_378.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378
ROUTE         3   e 1.081 */SLICE_378.F0 to */SLICE_171.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_165.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_78 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_78.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 0.280 */SLICE_344.Q0 to */SLICE_344.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_344.B0 to */SLICE_344.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344
ROUTE         8   e 1.081 */SLICE_344.F0 to */SLICE_169.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_80 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_80.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.248ns delay mg5ahub/SLICE_569 to mg5ahub/SLICE_82 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_569.CLK to */SLICE_569.Q0 mg5ahub/SLICE_569 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_569.Q0 to */SLICE_569.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.260 */SLICE_569.A0 to */SLICE_569.F0 mg5ahub/SLICE_569
ROUTE        10   e 1.081 */SLICE_569.F0 to *b/SLICE_82.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    2.248ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (2.004ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_122.CLK to */SLICE_122.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c)
ROUTE         4   e 1.081 */SLICE_122.Q1 to */SLICE_112.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.260 */SLICE_112.D1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.004   (32.1% logic, 67.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_168.CLK to */SLICE_168.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_168.Q0 to */SLICE_321.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]
CTOOFX_DEL  ---     0.494 */SLICE_321.C0 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay mg5ahub/SLICE_72 to mg5ahub/SLICE_73 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_72.CLK to *b/SLICE_72.Q0 mg5ahub/SLICE_72 (from jtaghub16_jtck)
ROUTE         4   e 1.081 *b/SLICE_72.Q0 to *b/SLICE_73.C1 mg5ahub/bit_count_2
CTOOFX_DEL  ---     0.494 *b/SLICE_73.C1 to *SLICE_73.OFX0 mg5ahub/SLICE_73
ROUTE         1   e 0.001 *SLICE_73.OFX0 to */SLICE_73.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_165.CLK to */SLICE_165.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_165.Q1 to */SLICE_318.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]
CTOOFX_DEL  ---     0.494 */SLICE_318.C0 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_169.CLK to */SLICE_169.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_169.Q0 to */SLICE_323.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]
CTOOFX_DEL  ---     0.494 */SLICE_323.C0 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_322.CLK to */SLICE_322.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_322.Q0 to */SLICE_321.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[12]
CTOOFX_DEL  ---     0.494 */SLICE_321.C1 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_73 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q1 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         5   e 1.081 *b/SLICE_71.Q1 to *b/SLICE_73.D1 mg5ahub/bit_count_1
CTOOFX_DEL  ---     0.494 *b/SLICE_73.D1 to *SLICE_73.OFX0 mg5ahub/SLICE_73
ROUTE         1   e 0.001 *SLICE_73.OFX0 to */SLICE_73.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_319.CLK to */SLICE_319.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_319.Q0 to */SLICE_318.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[7]
CTOOFX_DEL  ---     0.494 */SLICE_318.C1 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_73 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to *b/SLICE_73.A0 mg5ahub/jshift_d1
CTOOFX_DEL  ---     0.494 *b/SLICE_73.A0 to *SLICE_73.OFX0 mg5ahub/SLICE_73
ROUTE         1   e 0.001 *SLICE_73.OFX0 to */SLICE_73.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.052ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (1.959ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_322.CLK to */SLICE_322.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_322.Q1 to */SLICE_323.C1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[14]
CTOOFX_DEL  ---     0.494 */SLICE_323.C1 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    1.959   (44.8% logic, 55.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.023ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_49 (1.930ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.790 *b/SLICE_51.C0 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.393 */SLICE_49.FCI to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.930   (85.3% logic, 14.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.017ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_48 (1.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.790 *b/SLICE_51.C0 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.081 */SLICE_49.FCI to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.924   (85.2% logic, 14.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.951ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (1.858ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to *u/SLICE_34.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF1_DEL   ---     0.393 *u/SLICE_34.B0 to *u/SLICE_34.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 *u/SLICE_34.F1 to */SLICE_34.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[0] (to jtaghub16_jtck)
                  --------
                    1.858   (41.8% logic, 58.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.941ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_50 (1.848ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.790 *b/SLICE_51.C0 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.393 */SLICE_50.FCI to *b/SLICE_50.F1 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F1 to */SLICE_50.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.848   (84.7% logic, 15.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.941ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.848ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q0 to *u/SLICE_33.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.790 *u/SLICE_33.B0 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_32.FCI to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.848   (84.7% logic, 15.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.941ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_49 (1.848ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q0 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_50.Q0 to *b/SLICE_50.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.790 *b/SLICE_50.C0 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.393 */SLICE_49.FCI to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.848   (84.7% logic, 15.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.935ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.842ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q0 to *u/SLICE_33.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.790 *u/SLICE_33.B0 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.081 */SLICE_32.FCI to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.842   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.935ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_48 (1.842ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q0 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_50.Q0 to *b/SLICE_50.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.790 *b/SLICE_50.C0 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.081 */SLICE_49.FCI to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.842   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.935ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_49 (1.842ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.790 *b/SLICE_51.C0 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.305 */SLICE_49.FCI to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.842   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.853ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_49 (1.760ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q0 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_50.Q0 to *b/SLICE_50.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.790 *b/SLICE_50.C0 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.305 */SLICE_49.FCI to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.760   (84.0% logic, 16.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.853ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.760ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q0 to *u/SLICE_33.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.790 *u/SLICE_33.B0 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_32.FCI to *u/SLICE_32.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F0 to */SLICE_32.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.760   (84.0% logic, 16.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.853ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_50 (1.760ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.790 *b/SLICE_51.C0 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.305 */SLICE_50.FCI to *b/SLICE_50.F0 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F0 to */SLICE_50.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.760   (84.0% logic, 16.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.853ns delay mg5ahub/SLICE_49 to mg5ahub/SLICE_48 (1.760ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_49.CLK to *b/SLICE_49.Q0 mg5ahub/SLICE_49 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_49.Q0 to *b/SLICE_49.C0 mg5ahub/rom_rd_addr_5
C0TOFCO_DE  ---     0.790 *b/SLICE_49.C0 to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.760   (84.0% logic, 16.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.853ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.760ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_32.Q0 to *u/SLICE_32.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]
C0TOFCO_DE  ---     0.790 *u/SLICE_32.B0 to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.760   (84.0% logic, 16.0% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_112.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.260 */SLICE_112.A0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.001 */SLICE_112.F0 to *SLICE_112.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_250.CLK to */SLICE_250.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_250.Q1 to */SLICE_140.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[7]
CTOF_DEL    ---     0.260 */SLICE_140.C0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_72 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to *b/SLICE_72.A0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 *b/SLICE_72.A0 to *b/SLICE_72.F0 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F0 to */SLICE_72.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_179.CLK to */SLICE_179.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_179.Q1 to */SLICE_180.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.260 */SLICE_180.A0 to */SLICE_180.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180
ROUTE         1   e 0.001 */SLICE_180.F0 to *SLICE_180.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_254.CLK to */SLICE_254.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_254.Q1 to */SLICE_144.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[15]
CTOF_DEL    ---     0.260 */SLICE_144.C0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_252.CLK to */SLICE_252.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_252.Q1 to */SLICE_142.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[11]
CTOF_DEL    ---     0.260 */SLICE_142.C0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_248.CLK to */SLICE_248.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_248.Q1 to */SLICE_138.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[3]
CTOF_DEL    ---     0.260 */SLICE_138.C0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_256.CLK to */SLICE_256.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_256.Q1 to */SLICE_146.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[19]
CTOF_DEL    ---     0.260 */SLICE_146.C0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_214.B1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_214.B1 to */SLICE_214.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F1 to *SLICE_214.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_115.Q0 to */SLICE_118.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_118.C0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_177.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_177.B0 to */SLICE_177.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177
ROUTE         1   e 0.001 */SLICE_177.F0 to *SLICE_177.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_118.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.260 */SLICE_118.A0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_255.CLK to */SLICE_255.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_255.Q1 to */SLICE_145.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[17]
CTOF_DEL    ---     0.260 */SLICE_145.C0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_167.CLK to */SLICE_167.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_167.Q1 to */SLICE_168.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.260 */SLICE_168.B0 to */SLICE_168.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168
ROUTE         1   e 0.001 */SLICE_168.F0 to *SLICE_168.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_253.CLK to */SLICE_253.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_253.Q1 to */SLICE_143.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[13]
CTOF_DEL    ---     0.260 */SLICE_143.C0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_165.CLK to */SLICE_165.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_165.Q1 to */SLICE_166.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]
CTOF_DEL    ---     0.260 */SLICE_166.B0 to */SLICE_166.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166
ROUTE         1   e 0.001 */SLICE_166.F0 to *SLICE_166.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_252.CLK to */SLICE_252.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_252.Q0 to */SLICE_141.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[10]
CTOF_DEL    ---     0.260 */SLICE_141.C1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_165.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_165.A1 to */SLICE_165.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165
ROUTE         1   e 0.001 */SLICE_165.F1 to *SLICE_165.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[7] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_249.CLK to */SLICE_249.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_249.Q1 to */SLICE_139.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[5]
CTOF_DEL    ---     0.260 */SLICE_139.C0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_178.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_178.B1 to */SLICE_178.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178
ROUTE         1   e 0.001 */SLICE_178.F1 to *SLICE_178.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[9] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_247.CLK to */SLICE_247.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_247.Q1 to */SLICE_137.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[1]
CTOF_DEL    ---     0.260 */SLICE_137.C0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_167.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_167.A1 to */SLICE_167.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167
ROUTE         1   e 0.001 */SLICE_167.F1 to *SLICE_167.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[11] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_175.CLK to */SLICE_175.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_175.Q1 to */SLICE_176.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]
CTOF_DEL    ---     0.260 */SLICE_176.A0 to */SLICE_176.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176
ROUTE         1   e 0.001 */SLICE_176.F0 to *SLICE_176.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_163.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_163.A1 to */SLICE_163.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F1 to *SLICE_163.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_169.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_169.A0 to */SLICE_169.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169
ROUTE         1   e 0.001 */SLICE_169.F0 to *SLICE_169.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_165.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_165.A0 to */SLICE_165.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165
ROUTE         1   e 0.001 */SLICE_165.F0 to *SLICE_165.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_176.CLK to */SLICE_176.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_176.Q0 to */SLICE_174.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.260 */SLICE_174.B0 to */SLICE_174.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F0 to *SLICE_174.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_162.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_162.A0 to */SLICE_162.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_172.A0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_172.A0 to */SLICE_172.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F0 to *SLICE_172.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_270.CLK to */SLICE_270.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_270.Q0 to */SLICE_160.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[46]
CTOF_DEL    ---     0.260 */SLICE_160.C0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_213.B1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_213.B1 to */SLICE_213.F1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F1 to *SLICE_213.DI1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_270.CLK to */SLICE_270.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_270.Q0 to */SLICE_159.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[46]
CTOF_DEL    ---     0.260 */SLICE_159.C1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_181.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_181.B0 to */SLICE_181.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181
ROUTE         1   e 0.001 */SLICE_181.F0 to *SLICE_181.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_269.CLK to */SLICE_269.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_269.Q1 to */SLICE_159.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[45]
CTOF_DEL    ---     0.260 */SLICE_159.C0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_72 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to *b/SLICE_72.B1 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 *b/SLICE_72.B1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_269.CLK to */SLICE_269.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_269.Q0 to */SLICE_158.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[44]
CTOF_DEL    ---     0.260 */SLICE_158.C1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_256.CLK to */SLICE_256.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_256.Q0 to */SLICE_145.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[18]
CTOF_DEL    ---     0.260 */SLICE_145.C1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_268.CLK to */SLICE_268.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_268.Q1 to */SLICE_158.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[43]
CTOF_DEL    ---     0.260 */SLICE_158.C0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_255.CLK to */SLICE_255.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_255.Q0 to */SLICE_144.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[16]
CTOF_DEL    ---     0.260 */SLICE_144.C1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_268.CLK to */SLICE_268.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_268.Q0 to */SLICE_157.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[42]
CTOF_DEL    ---     0.260 */SLICE_157.C1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_254.CLK to */SLICE_254.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_254.Q0 to */SLICE_143.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[14]
CTOF_DEL    ---     0.260 */SLICE_143.C1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_267.CLK to */SLICE_267.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_267.Q1 to */SLICE_157.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[41]
CTOF_DEL    ---     0.260 */SLICE_157.C0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_253.CLK to */SLICE_253.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_253.Q0 to */SLICE_142.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[12]
CTOF_DEL    ---     0.260 */SLICE_142.C1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_267.CLK to */SLICE_267.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_267.Q0 to */SLICE_156.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[40]
CTOF_DEL    ---     0.260 */SLICE_156.C1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_251.CLK to */SLICE_251.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_251.Q1 to */SLICE_141.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[9]
CTOF_DEL    ---     0.260 */SLICE_141.C0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_266.CLK to */SLICE_266.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_266.Q1 to */SLICE_156.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[39]
CTOF_DEL    ---     0.260 */SLICE_156.C0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_251.CLK to */SLICE_251.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_251.Q0 to */SLICE_140.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[8]
CTOF_DEL    ---     0.260 */SLICE_140.C1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_266.CLK to */SLICE_266.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_266.Q0 to */SLICE_155.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[38]
CTOF_DEL    ---     0.260 */SLICE_155.C1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_250.CLK to */SLICE_250.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_250.Q0 to */SLICE_139.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[6]
CTOF_DEL    ---     0.260 */SLICE_139.C1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_265.CLK to */SLICE_265.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_265.Q1 to */SLICE_155.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[37]
CTOF_DEL    ---     0.260 */SLICE_155.C0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_249.CLK to */SLICE_249.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_249.Q0 to */SLICE_138.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[4]
CTOF_DEL    ---     0.260 */SLICE_138.C1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_265.CLK to */SLICE_265.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_265.Q0 to */SLICE_154.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[36]
CTOF_DEL    ---     0.260 */SLICE_154.C1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_248.CLK to */SLICE_248.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_248.Q0 to */SLICE_137.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[2]
CTOF_DEL    ---     0.260 */SLICE_137.C1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_264.CLK to */SLICE_264.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_264.Q1 to */SLICE_154.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[35]
CTOF_DEL    ---     0.260 */SLICE_154.C0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_169.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_169.A1 to */SLICE_169.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169
ROUTE         1   e 0.001 */SLICE_169.F1 to *SLICE_169.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[15] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_264.CLK to */SLICE_264.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_264.Q0 to */SLICE_153.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[34]
CTOF_DEL    ---     0.260 */SLICE_153.C1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_177.CLK to */SLICE_177.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_177.Q1 to */SLICE_178.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]
CTOF_DEL    ---     0.260 */SLICE_178.A0 to */SLICE_178.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178
ROUTE         1   e 0.001 */SLICE_178.F0 to *SLICE_178.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_263.CLK to */SLICE_263.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_263.Q1 to */SLICE_153.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[33]
CTOF_DEL    ---     0.260 */SLICE_153.C0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_175.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_175.B0 to */SLICE_175.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175
ROUTE         1   e 0.001 */SLICE_175.F0 to *SLICE_175.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_263.CLK to */SLICE_263.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_263.Q0 to */SLICE_152.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[32]
CTOF_DEL    ---     0.260 */SLICE_152.C1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_180.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_180.B1 to */SLICE_180.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180
ROUTE         1   e 0.001 */SLICE_180.F1 to *SLICE_180.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[13] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_262.CLK to */SLICE_262.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_262.Q1 to */SLICE_152.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[31]
CTOF_DEL    ---     0.260 */SLICE_152.C0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_167.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_167.A0 to */SLICE_167.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167
ROUTE         1   e 0.001 */SLICE_167.F0 to *SLICE_167.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_262.CLK to */SLICE_262.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_262.Q0 to */SLICE_151.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[30]
CTOF_DEL    ---     0.260 */SLICE_151.C1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_163.CLK to */SLICE_163.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_163.Q1 to */SLICE_164.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]
CTOF_DEL    ---     0.260 */SLICE_164.B0 to */SLICE_164.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164
ROUTE         1   e 0.001 */SLICE_164.F0 to *SLICE_164.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_261.CLK to */SLICE_261.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_261.Q1 to */SLICE_151.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[29]
CTOF_DEL    ---     0.260 */SLICE_151.C0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_163.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_163.A0 to */SLICE_163.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_261.CLK to */SLICE_261.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_261.Q0 to */SLICE_150.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[28]
CTOF_DEL    ---     0.260 */SLICE_150.C1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_173.A0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_173.A0 to */SLICE_173.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F0 to *SLICE_173.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_260.CLK to */SLICE_260.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_260.Q1 to */SLICE_150.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[27]
CTOF_DEL    ---     0.260 */SLICE_150.C0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_171.A0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_171.A0 to */SLICE_171.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F0 to *SLICE_171.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_260.CLK to */SLICE_260.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_260.Q0 to */SLICE_149.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[26]
CTOF_DEL    ---     0.260 */SLICE_149.C1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_211.A0 top_reveal_coretop_instance/top_la0_inst_0/addr[15]
CTOF_DEL    ---     0.260 */SLICE_211.A0 to */SLICE_211.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211
ROUTE         2   e 0.001 */SLICE_211.F0 to *SLICE_211.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_259.CLK to */SLICE_259.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_259.Q1 to */SLICE_149.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[25]
CTOF_DEL    ---     0.260 */SLICE_149.C0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_72 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q1 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         5   e 1.081 *b/SLICE_71.Q1 to *b/SLICE_72.C0 mg5ahub/bit_count_1
CTOF_DEL    ---     0.260 *b/SLICE_72.C0 to *b/SLICE_72.F0 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F0 to */SLICE_72.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_259.CLK to */SLICE_259.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_259.Q0 to */SLICE_148.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[24]
CTOF_DEL    ---     0.260 */SLICE_148.C1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_71 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to *b/SLICE_71.C1 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 *b/SLICE_71.C1 to *b/SLICE_71.F1 mg5ahub/SLICE_71
ROUTE         1   e 0.001 *b/SLICE_71.F1 to */SLICE_71.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_258.CLK to */SLICE_258.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_258.Q1 to */SLICE_148.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[23]
CTOF_DEL    ---     0.260 */SLICE_148.C0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_179.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_179.B0 to */SLICE_179.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179
ROUTE         1   e 0.001 */SLICE_179.F0 to *SLICE_179.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_258.CLK to */SLICE_258.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_258.Q0 to */SLICE_147.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[22]
CTOF_DEL    ---     0.260 */SLICE_147.C1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_174.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_174.B1 to */SLICE_174.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F1 to *SLICE_174.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[1] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_257.CLK to */SLICE_257.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_257.Q1 to */SLICE_147.C0 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[21]
CTOF_DEL    ---     0.260 */SLICE_147.C0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_257.CLK to */SLICE_257.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_257.Q0 to */SLICE_146.C1 top_reveal_coretop_instance/top_la0_inst_0/trace_dout[20]
CTOF_DEL    ---     0.260 */SLICE_146.C1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_176.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_176.B1 to */SLICE_176.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176
ROUTE         1   e 0.001 */SLICE_176.F1 to *SLICE_176.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[5] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_292 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_292.CLK to */SLICE_292.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_292 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_292.Q0 to */SLICE_284.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]
CTOF_DEL    ---     0.260 */SLICE_284.C0 to */SLICE_284.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F0 to *SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_304.Q0 to */SLICE_314.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_314.C0 to */SLICE_314.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to *u/SLICE_31.A0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 *u/SLICE_31.A0 to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_161.Q0 to */SLICE_112.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_112.C0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.001 */SLICE_112.F0 to *SLICE_112.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_299.CLK to */SLICE_299.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_299.Q0 to */SLICE_291.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]
CTOF_DEL    ---     0.260 */SLICE_291.C0 to */SLICE_291.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F0 to *SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_298.CLK to */SLICE_298.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_298.Q0 to */SLICE_290.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]
CTOF_DEL    ---     0.260 */SLICE_290.C0 to */SLICE_290.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F0 to *SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_297.CLK to */SLICE_297.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_297.Q0 to */SLICE_289.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]
CTOF_DEL    ---     0.260 */SLICE_289.C0 to */SLICE_289.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_296 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_296.CLK to */SLICE_296.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_296 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_296.Q0 to */SLICE_288.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]
CTOF_DEL    ---     0.260 */SLICE_288.C0 to */SLICE_288.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_295 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_295.CLK to */SLICE_295.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_295 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_295.Q0 to */SLICE_287.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]
CTOF_DEL    ---     0.260 */SLICE_287.C0 to */SLICE_287.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_294 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_294.CLK to */SLICE_294.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_294 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_294.Q0 to */SLICE_286.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]
CTOF_DEL    ---     0.260 */SLICE_286.C0 to */SLICE_286.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_293 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_293.CLK to */SLICE_293.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_293 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_293.Q0 to */SLICE_285.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]
CTOF_DEL    ---     0.260 */SLICE_285.C0 to */SLICE_285.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F0 to *SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_549.CLK to */SLICE_549.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_549 (from ipClk_c)
ROUTE         5   e 1.081 */SLICE_549.Q0 to */SLICE_184.A0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
CTOF_DEL    ---     0.260 */SLICE_184.A0 to */SLICE_184.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184
ROUTE         1   e 0.001 */SLICE_184.F0 to *SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_164.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_164.A1 to */SLICE_164.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164
ROUTE         1   e 0.001 */SLICE_164.F1 to *SLICE_164.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[5] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_144.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_144.B0 to */SLICE_144.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_143.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_143.B1 to */SLICE_143.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_143.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_143.B0 to */SLICE_143.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_142.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_142.B0 to */SLICE_142.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_141.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_141.B0 to */SLICE_141.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_141.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_141.B1 to */SLICE_141.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_140.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_140.B1 to */SLICE_140.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F1 to *SLICE_140.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_140.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_140.B0 to */SLICE_140.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_139.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_139.B1 to */SLICE_139.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F1 to *SLICE_139.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_139.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_139.B0 to */SLICE_139.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_138.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_138.B1 to */SLICE_138.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_137.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_137.B1 to */SLICE_137.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_137.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_137.B0 to */SLICE_137.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_168.CLK to */SLICE_168.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_168.Q1 to */SLICE_169.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]
CTOF_DEL    ---     0.260 */SLICE_169.B0 to */SLICE_169.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169
ROUTE         1   e 0.001 */SLICE_169.F0 to *SLICE_169.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_166.CLK to */SLICE_166.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_166.Q1 to */SLICE_167.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]
CTOF_DEL    ---     0.260 */SLICE_167.B0 to */SLICE_167.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167
ROUTE         1   e 0.001 */SLICE_167.F0 to *SLICE_167.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_150.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_150.B0 to */SLICE_150.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_149.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_149.B1 to */SLICE_149.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F1 to *SLICE_149.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_118.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_118.B0 to */SLICE_118.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         6   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_152.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_152.B0 to */SLICE_152.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_142.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_142.B1 to */SLICE_142.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_138.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_138.B0 to */SLICE_138.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_166.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_166.A1 to */SLICE_166.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166
ROUTE         1   e 0.001 */SLICE_166.F1 to *SLICE_166.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[9] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_162.CLK to */SLICE_162.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_162.Q1 to */SLICE_163.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]
CTOF_DEL    ---     0.260 */SLICE_163.B0 to */SLICE_163.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_178.CLK to */SLICE_178.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_178.Q1 to */SLICE_179.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]
CTOF_DEL    ---     0.260 */SLICE_179.A0 to */SLICE_179.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179
ROUTE         1   e 0.001 */SLICE_179.F0 to *SLICE_179.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_178.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_178.B0 to */SLICE_178.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178
ROUTE         1   e 0.001 */SLICE_178.F0 to *SLICE_178.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_176.CLK to */SLICE_176.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_176.Q1 to */SLICE_177.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]
CTOF_DEL    ---     0.260 */SLICE_177.A0 to */SLICE_177.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177
ROUTE         1   e 0.001 */SLICE_177.F0 to *SLICE_177.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_215.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_215.B0 to */SLICE_215.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215
ROUTE         1   e 0.001 */SLICE_215.F0 to *SLICE_215.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_72 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q0 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         6   e 1.081 *b/SLICE_71.Q0 to *b/SLICE_72.D0 mg5ahub/bit_count_0
CTOF_DEL    ---     0.260 *b/SLICE_72.D0 to *b/SLICE_72.F0 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F0 to */SLICE_72.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_179.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_179.B1 to */SLICE_179.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179
ROUTE         1   e 0.001 */SLICE_179.F1 to *SLICE_179.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[11] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_176.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_176.B0 to */SLICE_176.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176
ROUTE         1   e 0.001 */SLICE_176.F0 to *SLICE_176.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_88 to mg5ahub/SLICE_71 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_88.CLK to *b/SLICE_88.Q0 mg5ahub/SLICE_88 (from jtaghub16_jtck)
ROUTE         7   e 1.081 *b/SLICE_88.Q0 to *b/SLICE_71.C0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.260 *b/SLICE_71.C0 to *b/SLICE_71.F0 mg5ahub/SLICE_71
ROUTE         1   e 0.001 *b/SLICE_71.F0 to */SLICE_71.DI0 mg5ahub/bit_count_3_iv_0_m4_0 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_153.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_153.B0 to */SLICE_153.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_151.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_151.B1 to */SLICE_151.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_150.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_150.B1 to */SLICE_150.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_144.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_144.B1 to */SLICE_144.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_177.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_177.B1 to */SLICE_177.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177
ROUTE         1   e 0.001 */SLICE_177.F1 to *SLICE_177.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[7] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_180.CLK to */SLICE_180.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_180.Q1 to */SLICE_181.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]
CTOF_DEL    ---     0.260 */SLICE_181.A0 to */SLICE_181.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181
ROUTE         1   e 0.001 */SLICE_181.F0 to *SLICE_181.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_180.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_180.B0 to */SLICE_180.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180
ROUTE         1   e 0.001 */SLICE_180.F0 to *SLICE_180.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_174.CLK to */SLICE_174.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_174.Q1 to */SLICE_175.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]
CTOF_DEL    ---     0.260 */SLICE_175.A0 to */SLICE_175.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175
ROUTE         1   e 0.001 */SLICE_175.F0 to *SLICE_175.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_124.CLK to */SLICE_124.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_124.Q0 to */SLICE_184.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker
CTOF_DEL    ---     0.260 */SLICE_184.C0 to */SLICE_184.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184
ROUTE         1   e 0.001 */SLICE_184.F0 to *SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_160.A0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_160.A0 to */SLICE_160.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_168.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_168.A1 to */SLICE_168.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168
ROUTE         1   e 0.001 */SLICE_168.F1 to *SLICE_168.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[13] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_175.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_175.B1 to */SLICE_175.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175
ROUTE         1   e 0.001 */SLICE_175.F1 to *SLICE_175.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_159.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_159.B1 to */SLICE_159.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_159.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_159.B0 to */SLICE_159.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_158.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_158.B1 to */SLICE_158.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_158.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_158.B0 to */SLICE_158.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_157.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_157.B1 to */SLICE_157.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_157.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_157.B0 to */SLICE_157.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_156.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_156.B1 to */SLICE_156.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_156.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_156.B0 to */SLICE_156.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_155.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_155.B1 to */SLICE_155.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_155.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_155.B0 to */SLICE_155.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_154.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_154.B1 to */SLICE_154.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_154.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_154.B0 to */SLICE_154.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_183.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_183.B0 to */SLICE_183.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.001 */SLICE_183.F0 to *SLICE_183.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_214.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_214.B0 to */SLICE_214.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214
ROUTE         1   e 0.001 */SLICE_214.F0 to *SLICE_214.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_213.B0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.260 */SLICE_213.B0 to */SLICE_213.F0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213
ROUTE         1   e 0.001 */SLICE_213.F0 to *SLICE_213.DI0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_73 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q0 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         6   e 1.081 *b/SLICE_71.Q0 to *b/SLICE_73.M0 mg5ahub/bit_count_0
MTOOFX_DEL  ---     0.260 *b/SLICE_73.M0 to *SLICE_73.OFX0 mg5ahub/SLICE_73
ROUTE         1   e 0.001 *SLICE_73.OFX0 to */SLICE_73.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_149.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_149.B0 to */SLICE_149.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149
ROUTE         1   e 0.001 */SLICE_149.F0 to *SLICE_149.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_148.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_148.B1 to */SLICE_148.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_148.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_148.B0 to */SLICE_148.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_147.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_147.B1 to */SLICE_147.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_147.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_147.B0 to */SLICE_147.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_146.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_146.B1 to */SLICE_146.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_146.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_146.B0 to */SLICE_146.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_145.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_145.B1 to */SLICE_145.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_145.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_145.B0 to */SLICE_145.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_168.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_168.A0 to */SLICE_168.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168
ROUTE         1   e 0.001 */SLICE_168.F0 to *SLICE_168.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_166.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_166.A0 to */SLICE_166.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166
ROUTE         1   e 0.001 */SLICE_166.F0 to *SLICE_166.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 1.081 */SLICE_182.Q0 to */SLICE_181.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_181.B1 to */SLICE_181.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181
ROUTE         1   e 0.001 */SLICE_181.F1 to *SLICE_181.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[15] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_179.CLK to */SLICE_179.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_179.Q1 to */SLICE_174.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.260 */SLICE_174.C0 to */SLICE_174.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F0 to *SLICE_174.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_164.CLK to */SLICE_164.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_164.Q1 to */SLICE_165.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]
CTOF_DEL    ---     0.260 */SLICE_165.B0 to */SLICE_165.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165
ROUTE         1   e 0.001 */SLICE_165.F0 to *SLICE_165.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_153.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_153.B1 to */SLICE_153.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_162.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_162.A1 to */SLICE_162.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F1 to *SLICE_162.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[1] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_152.B1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_152.B1 to */SLICE_152.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_173.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_173.A1 to */SLICE_173.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173
ROUTE         1   e 0.001 */SLICE_173.F1 to *SLICE_173.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_151.B0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_151.B0 to */SLICE_151.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_172.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_172.A1 to */SLICE_172.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172
ROUTE         1   e 0.001 */SLICE_172.F1 to *SLICE_172.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_171.A1 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.260 */SLICE_171.A1 to */SLICE_171.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171
ROUTE         1   e 0.001 */SLICE_171.F1 to *SLICE_171.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_344.CLK to */SLICE_344.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (from jtaghub16_jtck)
ROUTE        17   e 1.081 */SLICE_344.Q0 to */SLICE_164.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.260 */SLICE_164.A0 to */SLICE_164.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164
ROUTE         1   e 0.001 */SLICE_164.F0 to *SLICE_164.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_297.CLK to */SLICE_297.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_297.Q1 to */SLICE_289.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]
CTOF_DEL    ---     0.260 */SLICE_289.C1 to */SLICE_289.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F1 to *SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_296 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_296.CLK to */SLICE_296.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_296 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_296.Q1 to */SLICE_288.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]
CTOF_DEL    ---     0.260 */SLICE_288.C1 to */SLICE_288.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_295 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_295.CLK to */SLICE_295.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_295 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_295.Q1 to */SLICE_287.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]
CTOF_DEL    ---     0.260 */SLICE_287.C1 to */SLICE_287.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F1 to *SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_294 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_294.CLK to */SLICE_294.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_294 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_294.Q1 to */SLICE_286.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]
CTOF_DEL    ---     0.260 */SLICE_286.C1 to */SLICE_286.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F1 to *SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_293 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_293.CLK to */SLICE_293.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_293 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_293.Q1 to */SLICE_285.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]
CTOF_DEL    ---     0.260 */SLICE_285.C1 to */SLICE_285.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285
ROUTE         1   e 0.001 */SLICE_285.F1 to *SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_292 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_292.CLK to */SLICE_292.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_292 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_292.Q1 to */SLICE_284.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]
CTOF_DEL    ---     0.260 */SLICE_284.C1 to */SLICE_284.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284
ROUTE         1   e 0.001 */SLICE_284.F1 to *SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_304.Q0 to */SLICE_302.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_302.C0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_299.CLK to */SLICE_299.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_299.Q1 to */SLICE_291.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]
CTOF_DEL    ---     0.260 */SLICE_291.C1 to */SLICE_291.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291
ROUTE         1   e 0.001 */SLICE_291.F1 to *SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_298.CLK to */SLICE_298.Q1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298 (from ipClk_c)
ROUTE         1   e 1.081 */SLICE_298.Q1 to */SLICE_290.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]
CTOF_DEL    ---     0.260 */SLICE_290.C1 to */SLICE_290.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290
ROUTE         1   e 0.001 */SLICE_290.F1 to *SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_412.CLK to */SLICE_412.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_412.Q0 to */SLICE_107.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.260 */SLICE_107.C0 to */SLICE_107.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107
ROUTE        14   e 0.001 */SLICE_107.F0 to *SLICE_107.DI0 top_reveal_coretop_instance/top_la0_inst_0/capture_dr (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_382.CLK to */SLICE_382.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (from jtaghub16_jtck)
ROUTE        26   e 1.081 */SLICE_382.Q0 to */SLICE_112.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.260 */SLICE_112.B0 to */SLICE_112.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         2   e 0.001 */SLICE_112.F0 to *SLICE_112.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.818ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (1.725ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_368.CLK to */SLICE_368.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_368.Q0 to */SLICE_314.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.260 */SLICE_314.A0 to */SLICE_314.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.725   (37.3% logic, 62.7% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.790ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_49 (1.697ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.081 */SLICE_51.FCI to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.393 */SLICE_49.FCI to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.697   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.784ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_48 (1.691ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.081 */SLICE_51.FCI to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.081 */SLICE_49.FCI to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.691   (83.1% logic, 16.9% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_382 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_382.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_123.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_315.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_319.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_322.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_113.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_412 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_412.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_108.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_184.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_321.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_182.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_120.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_344.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_115.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_119.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_316.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_317.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_183.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_320.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_107.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_130.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_539.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_323.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_318.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_124.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_161.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay SLICE_572 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (1.464ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383  SLICE_572.CLK to   SLICE_572.Q0 SLICE_572 (from jtaghub16_jtck)
ROUTE        53   e 1.081   SLICE_572.Q0 to */SLICE_118.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_49 (1.615ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.475 *b/SLICE_51.C1 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.393 */SLICE_49.FCI to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.615   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_50 (1.615ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.081 */SLICE_51.FCI to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.393 */SLICE_50.FCI to *b/SLICE_50.F1 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F1 to */SLICE_50.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.615   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.708ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.615ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_34.B1 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_32.FCI to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.615   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.702ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_49 (1.609ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.081 */SLICE_51.FCI to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.305 */SLICE_49.FCI to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.609   (82.3% logic, 17.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.702ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.609ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_34.B1 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.081 */SLICE_32.FCI to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.609   (82.3% logic, 17.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.702ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_48 (1.609ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.475 *b/SLICE_51.C1 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.081 */SLICE_49.FCI to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.609   (82.3% logic, 17.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO27 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO27 to */SLICE_269.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[45] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO25 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO25 to */SLICE_268.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[43] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO23 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO23 to */SLICE_267.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[41] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO21 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO21 to */SLICE_266.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[39] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO19 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO19 to */SLICE_265.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[37] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO17 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO17 to */SLICE_264.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[35] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO15 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO15 to */SLICE_263.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[33] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO13 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO13 to */SLICE_262.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[31] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO11 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO11 to */SLICE_261.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[29] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO9 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO9 to */SLICE_260.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[27] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO7 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO7 to */SLICE_259.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[25] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO5 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO5 to */SLICE_258.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[23] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO3 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO3 to */SLICE_257.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[21] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO1 to */SLICE_256.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[19] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO35 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO35 to */SLICE_255.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[17] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO33 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO33 to */SLICE_254.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[15] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO31 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO31 to */SLICE_253.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[13] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO29 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO29 to */SLICE_252.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[11] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO27 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO27 to */SLICE_251.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[9] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO25 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO25 to */SLICE_250.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[7] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO23 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO23 to */SLICE_249.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[5] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO21 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO21 to */SLICE_248.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[3] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO19 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO19 to */SLICE_247.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[1] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_248 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO20 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO20 to */SLICE_248.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[2] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_269 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO26 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO26 to */SLICE_269.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[44] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_268 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO24 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO24 to */SLICE_268.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[42] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_267 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO22 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO22 to */SLICE_267.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[40] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_266 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO20 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO20 to */SLICE_266.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[38] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_265 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO18 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO18 to */SLICE_265.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[36] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_264 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO16 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO16 to */SLICE_264.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[34] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_247 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO18 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO18 to */SLICE_247.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[0] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_262 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO12 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO12 to */SLICE_262.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[30] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_261 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO10 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO10 to */SLICE_261.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[28] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_260 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO8 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO8 to */SLICE_260.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[26] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_270 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_1_0.CLKR to *97_0_1_0.DO28 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_1_0.DO28 to */SLICE_270.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[46] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_258 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO4 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO4 to */SLICE_258.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[22] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_257 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO2 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO2 to */SLICE_257.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[20] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_256 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO0 to */SLICE_256.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[18] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_255 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO34 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO34 to */SLICE_255.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[16] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_254 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO32 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO32 to */SLICE_254.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[14] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_253 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO30 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO30 to */SLICE_253.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[12] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_252 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO28 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO28 to */SLICE_252.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[10] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_251 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO26 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO26 to */SLICE_251.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[8] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_250 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO24 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO24 to */SLICE_250.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[6] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_249 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO22 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO22 to */SLICE_249.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[4] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_259 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *a97_0_0_1.DO6 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *a97_0_0_1.DO6 to */SLICE_259.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[24] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.685ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_263 (1.537ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.456 *97_0_0_1.CLKR to *97_0_0_1.DO14 top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *97_0_0_1.DO14 to */SLICE_263.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[32] (to jtaghub16_jtck)
                  --------
                    1.537   (29.7% logic, 70.3% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.626ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.533ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q1 to *u/SLICE_33.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.475 *u/SLICE_33.B1 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.393 */SLICE_32.FCI to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.533   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.626ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_51 (1.533ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOF1_DE  ---     0.393 */SLICE_51.FCI to *b/SLICE_51.F1 mg5ahub/SLICE_51
ROUTE         1   e 0.001 *b/SLICE_51.F1 to */SLICE_51.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    1.533   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.626ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_49 (1.533ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q1 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_50.Q1 to *b/SLICE_50.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.475 *b/SLICE_50.C1 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.393 */SLICE_49.FCI to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.533   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.626ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (1.533ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_34.B1 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF1_DE  ---     0.393 */SLICE_33.FCI to *u/SLICE_33.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F1 to */SLICE_33.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    1.533   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.626ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_50 (1.533ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.475 *b/SLICE_51.C1 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.393 */SLICE_50.FCI to *b/SLICE_50.F1 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F1 to */SLICE_50.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.533   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.620ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.527ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_34.B1 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.081 */SLICE_33.FCI to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_32.FCI to *u/SLICE_32.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F0 to */SLICE_32.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.527   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.620ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_49 (1.527ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.475 *b/SLICE_51.C1 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.081 */SLICE_50.FCI to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.305 */SLICE_49.FCI to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.527   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.620ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_48 (1.527ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q1 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_50.Q1 to *b/SLICE_50.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.475 *b/SLICE_50.C1 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.081 */SLICE_49.FCI to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.527   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.620ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.527ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q1 to *u/SLICE_33.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.475 *u/SLICE_33.B1 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.081 */SLICE_32.FCI to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.527   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.620ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_50 (1.527ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.081 */SLICE_51.FCI to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.305 */SLICE_50.FCI to *b/SLICE_50.F0 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F0 to */SLICE_50.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.527   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_75 to SLICE_572 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_75.CLK to *b/SLICE_75.Q1 mg5ahub/SLICE_75 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_75.Q1 to   SLICE_572.M0 mg5ahub/er1_shift_reg_4 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_97.Q0 to */SLICE_127.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[8] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to *u/SLICE_95.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[4] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 1.081 */SLICE_115.Q1 to */SLICE_368.M0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        11   e 1.081 *u/SLICE_96.Q0 to */SLICE_134.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[4] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_100.Q0 to */SLICE_135.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_128.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_408 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_345.CLK to */SLICE_345.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_345.Q0 to */SLICE_408.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_128.CLK to */SLICE_128.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_128.Q0 to */SLICE_100.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_463 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        39   e 1.081 *u/SLICE_94.Q0 to */SLICE_463.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[0] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_135 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_135.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_344.M0 top_reveal_coretop_instance/top_la0_inst_0/addr_15 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 1.081 *u/SLICE_94.Q1 to */SLICE_133.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[1] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_107.CLK to */SLICE_107.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_107.Q1 to */SLICE_108.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        20   e 1.081 *u/SLICE_99.Q0 to *u/SLICE_98.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[12] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_113.Q1 to */SLICE_539.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_75 to mg5ahub/SLICE_74 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_75.CLK to *b/SLICE_75.Q0 mg5ahub/SLICE_75 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_75.Q0 to *b/SLICE_74.M1 mg5ahub/er1_shift_reg_3 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_119.CLK to */SLICE_119.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_119.Q1 to */SLICE_120.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_424.CLK to */SLICE_424.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (from jtaghub16_jtck)
ROUTE        21   e 1.081 */SLICE_424.Q0 to */SLICE_378.M0 top_reveal_coretop_instance/top_la0_inst_0/addr_15 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_77 to mg5ahub/SLICE_86 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_77.CLK to *b/SLICE_77.Q1 mg5ahub/SLICE_77 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_77.Q1 to *b/SLICE_86.M1 mg5ahub/er1_shift_reg_8 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_81 to mg5ahub/SLICE_80 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_81.CLK to *b/SLICE_81.Q0 mg5ahub/SLICE_81 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_81.Q0 to *b/SLICE_80.M1 mg5ahub/er1_shift_reg_15 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_83 to mg5ahub/SLICE_82 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_83.CLK to *b/SLICE_83.Q0 mg5ahub/SLICE_83 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_83.Q0 to *b/SLICE_82.M1 mg5ahub/er1_shift_reg_19 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_76 to mg5ahub/SLICE_85 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_76.CLK to *b/SLICE_76.Q0 mg5ahub/SLICE_76 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_76.Q0 to *b/SLICE_85.M0 mg5ahub/er1_shift_reg_5 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_79 to mg5ahub/SLICE_78 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_79.CLK to *b/SLICE_79.Q0 mg5ahub/SLICE_79 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_79.Q0 to *b/SLICE_78.M1 mg5ahub/er1_shift_reg_11 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_77 to mg5ahub/SLICE_76 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_77.CLK to *b/SLICE_77.Q0 mg5ahub/SLICE_77 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_77.Q0 to *b/SLICE_76.M1 mg5ahub/er1_shift_reg_7 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_76 to mg5ahub/SLICE_75 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_76.CLK to *b/SLICE_76.Q0 mg5ahub/SLICE_76 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_76.Q0 to *b/SLICE_75.M1 mg5ahub/er1_shift_reg_5 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_82 to mg5ahub/SLICE_81 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_82.CLK to *b/SLICE_82.Q0 mg5ahub/SLICE_82 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_82.Q0 to *b/SLICE_81.M1 mg5ahub/er1_shift_reg_17 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_77 to mg5ahub/SLICE_86 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_77.CLK to *b/SLICE_77.Q0 mg5ahub/SLICE_77 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_77.Q0 to *b/SLICE_86.M0 mg5ahub/er1_shift_reg_7 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_80 to mg5ahub/SLICE_79 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_80.CLK to *b/SLICE_80.Q0 mg5ahub/SLICE_80 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_80.Q0 to *b/SLICE_79.M1 mg5ahub/er1_shift_reg_13 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_76 to mg5ahub/SLICE_85 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_76.CLK to *b/SLICE_76.Q1 mg5ahub/SLICE_76 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_76.Q1 to *b/SLICE_85.M1 mg5ahub/er1_shift_reg_6 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_78 to mg5ahub/SLICE_77 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_78.CLK to *b/SLICE_78.Q0 mg5ahub/SLICE_78 (from jtaghub16_jtck)
ROUTE         1   e 1.081 *b/SLICE_78.Q0 to *b/SLICE_77.M1 mg5ahub/er1_shift_reg_9 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_424 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_424.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[15] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_108.CLK to */SLICE_108.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_108.Q0 to */SLICE_109.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_118.CLK to */SLICE_118.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_118.Q1 to */SLICE_119.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_100.Q0 to */SLICE_136.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_100.Q0 to *u/SLICE_99.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_548 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_184.CLK to */SLICE_184.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184 (from jtaghub16_jtck)
ROUTE         4   e 1.081 */SLICE_184.Q0 to */SLICE_548.M0 top_reveal_coretop_instance/top_la0_inst_0/parity_err (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_405 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         6   e 1.081 */SLICE_100.Q0 to */SLICE_405.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_127.CLK to */SLICE_127.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (from jtaghub16_jtck)
ROUTE         1   e 1.081 */SLICE_127.Q0 to *u/SLICE_96.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_456 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_456.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_136 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 1.081 *u/SLICE_99.Q1 to */SLICE_136.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_133 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to */SLICE_133.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[2] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 to top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_130.CLK to */SLICE_130.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (from jtaghub16_jtck)
ROUTE         2   e 1.081 */SLICE_130.Q0 to */SLICE_345.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_134 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        16   e 1.081 *u/SLICE_95.Q1 to */SLICE_134.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[3] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 1.081 *u/SLICE_98.Q0 to *u/SLICE_97.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[10] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_410 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 1.081 */SLICE_100.Q1 to */SLICE_410.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[15] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_211.CLK to */SLICE_211.Q0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_211 (from jtaghub16_jtck)
ROUTE         7   e 1.081 */SLICE_211.Q0 to */SLICE_212.M0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay mg5ahub/SLICE_83 to mg5ahub/SLICE_341 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_83.CLK to *b/SLICE_83.Q1 mg5ahub/SLICE_83 (from jtaghub16_jtck)
ROUTE         2   e 1.081 *b/SLICE_83.Q1 to */SLICE_341.M0 mg5ahub/er1_shift_reg_20 (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.612ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (1.464ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        31   e 1.081 *u/SLICE_95.Q0 to *u/SLICE_94.M1 top_reveal_coretop_instance/top_la0_inst_0/addr[2] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.557ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (1.464ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_302.CLK to */SLICE_302.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_302.Q0 to */SLICE_302.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.260 */SLICE_302.C1 to */SLICE_302.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE        20   e 0.280 */SLICE_302.F1 to */SLICE_302.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_77
CTOF_DEL    ---     0.260 */SLICE_302.A0 to */SLICE_302.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302
ROUTE         1   e 0.001 */SLICE_302.F0 to *SLICE_302.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i (to jtaghub16_jtck)
                  --------
                    1.464   (61.7% logic, 38.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.557ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (1.464ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_182.CLK to */SLICE_182.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182 (from jtaghub16_jtck)
ROUTE        18   e 0.280 */SLICE_182.Q0 to */SLICE_182.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.260 */SLICE_182.B1 to */SLICE_182.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.280 */SLICE_182.F1 to */SLICE_182.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a4_0_1
CTOF_DEL    ---     0.260 */SLICE_182.D0 to */SLICE_182.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182
ROUTE         1   e 0.001 */SLICE_182.F0 to *SLICE_182.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    1.464   (61.7% logic, 38.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_51 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.475 *b/SLICE_47.C1 to */SLICE_47.FCO mg5ahub/SLICE_47
ROUTE         1   e 0.001 */SLICE_47.FCO to */SLICE_51.FCI mg5ahub/rom_rd_addr_cry_0
FCITOF0_DE  ---     0.305 */SLICE_51.FCI to *b/SLICE_51.F0 mg5ahub/SLICE_51
ROUTE         1   e 0.001 *b/SLICE_51.F0 to */SLICE_51.DI0 mg5ahub/rom_rd_addr_s_1 (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_49 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q1 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_50.Q1 to *b/SLICE_50.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.475 *b/SLICE_50.C1 to */SLICE_50.FCO mg5ahub/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.305 */SLICE_49.FCI to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q1 to *u/SLICE_33.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.475 *u/SLICE_33.B1 to */SLICE_33.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 */SLICE_33.FCO to */SLICE_32.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.305 */SLICE_32.FCI to *u/SLICE_32.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F0 to */SLICE_32.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay mg5ahub/SLICE_49 to mg5ahub/SLICE_48 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_49.CLK to *b/SLICE_49.Q1 mg5ahub/SLICE_49 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_49.Q1 to *b/SLICE_49.C1 mg5ahub/rom_rd_addr_6
C1TOFCO_DE  ---     0.475 *b/SLICE_49.C1 to */SLICE_49.FCO mg5ahub/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.305 */SLICE_48.FCI to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.475 *u/SLICE_34.B1 to */SLICE_34.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 */SLICE_34.FCO to */SLICE_33.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF0_DE  ---     0.305 */SLICE_33.FCI to *u/SLICE_33.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F0 to */SLICE_33.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         4   e 0.280 *u/SLICE_32.Q1 to *u/SLICE_32.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]
C1TOFCO_DE  ---     0.475 *u/SLICE_32.B1 to */SLICE_32.FCO top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 */SLICE_32.FCO to */SLICE_31.FCI top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.305 */SLICE_31.FCI to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.538ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_50 (1.445ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.475 *b/SLICE_51.C1 to */SLICE_51.FCO mg5ahub/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.305 */SLICE_50.FCI to *b/SLICE_50.F0 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F0 to */SLICE_50.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.445   (80.5% logic, 19.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.447ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (1.203ns delay and 0.244ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_112.CLK to */SLICE_112.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_112.Q0 to */SLICE_112.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.260 */SLICE_112.A1 to */SLICE_112.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112
ROUTE         1   e 0.280 */SLICE_112.F1 to */SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    1.203   (53.4% logic, 46.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q0 to *97_0_1_0.ADR7 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_215.CLK to */SLICE_215.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_215.Q0 to *97_0_1_0.ADR9 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *97_0_1_0.ADR5 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *97_0_1_0.ADR6 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q1 to *97_0_1_0.ADR8 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q0 to *97_0_0_1.ADR5 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_213.CLK to */SLICE_213.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_213.Q1 to *97_0_0_1.ADR6 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q0 to *97_0_0_1.ADR7 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_214.CLK to */SLICE_214.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_214.Q1 to *97_0_0_1.ADR8 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.307ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 (1.464ns delay and -0.157ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_215.CLK to */SLICE_215.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215 (from jtaghub16_jtck)
ROUTE         3   e 1.081 */SLICE_215.Q0 to *97_0_0_1.ADR9 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4] (to jtaghub16_jtck)
                  --------
                    1.464   (26.2% logic, 73.8% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.251ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (1.158ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_318.CLK to */SLICE_318.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_318.Q0 to */SLICE_318.B1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[6]
CTOOFX_DEL  ---     0.494 */SLICE_318.B1 to *LICE_318.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318
ROUTE         1   e 0.001 *LICE_318.OFX0 to *SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6] (to jtaghub16_jtck)
                  --------
                    1.158   (75.7% logic, 24.3% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.251ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (1.158ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_323.CLK to */SLICE_323.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_323.Q0 to */SLICE_323.B1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[13]
CTOOFX_DEL  ---     0.494 */SLICE_323.B1 to *LICE_323.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323
ROUTE         1   e 0.001 *LICE_323.OFX0 to *SLICE_323.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56 (to jtaghub16_jtck)
                  --------
                    1.158   (75.7% logic, 24.3% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.251ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (1.158ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_321.CLK to */SLICE_321.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_321.Q0 to */SLICE_321.B1 top_reveal_coretop_instance/top_la0_inst_0/wr_din[11]
CTOOFX_DEL  ---     0.494 */SLICE_321.B1 to *LICE_321.OFX0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321
ROUTE         1   e 0.001 *LICE_321.OFX0 to *SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57 (to jtaghub16_jtck)
                  --------
                    1.158   (75.7% logic, 24.3% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.251ns delay mg5ahub/SLICE_73 to mg5ahub/SLICE_73 (1.158ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_73.CLK to *b/SLICE_73.Q0 mg5ahub/SLICE_73 (from jtaghub16_jtck)
ROUTE         4   e 0.280 *b/SLICE_73.Q0 to *b/SLICE_73.B0 mg5ahub/bit_count_3
CTOOFX_DEL  ---     0.494 *b/SLICE_73.B0 to *SLICE_73.OFX0 mg5ahub/SLICE_73
ROUTE         1   e 0.001 *SLICE_73.OFX0 to */SLICE_73.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.158   (75.7% logic, 24.3% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.150ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (1.057ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q0 to *u/SLICE_33.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF1_DEL   ---     0.393 *u/SLICE_33.B0 to *u/SLICE_33.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F1 to */SLICE_33.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    1.057   (73.4% logic, 26.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.150ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_50 (1.057ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q0 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_50.Q0 to *b/SLICE_50.C0 mg5ahub/rom_rd_addr_3
CTOF1_DEL   ---     0.393 *b/SLICE_50.C0 to *b/SLICE_50.F1 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F1 to */SLICE_50.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.057   (73.4% logic, 26.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.150ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_51 (1.057ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
CTOF1_DEL   ---     0.393 *b/SLICE_51.C0 to *b/SLICE_51.F1 mg5ahub/SLICE_51
ROUTE         1   e 0.001 *b/SLICE_51.F1 to */SLICE_51.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    1.057   (73.4% logic, 26.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.150ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (1.057ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_32.Q0 to *u/SLICE_32.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF1_DEL   ---     0.393 *u/SLICE_32.B0 to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.057   (73.4% logic, 26.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.150ns delay mg5ahub/SLICE_49 to mg5ahub/SLICE_49 (1.057ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_49.CLK to *b/SLICE_49.Q0 mg5ahub/SLICE_49 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_49.Q0 to *b/SLICE_49.C0 mg5ahub/rom_rd_addr_5
CTOF1_DEL   ---     0.393 *b/SLICE_49.C0 to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.057   (73.4% logic, 26.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_168.CLK to */SLICE_168.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_168.Q0 to */SLICE_168.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]
CTOF_DEL    ---     0.260 */SLICE_168.B1 to */SLICE_168.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168
ROUTE         1   e 0.001 */SLICE_168.F1 to *SLICE_168.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[13] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_164.CLK to */SLICE_164.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_164.Q0 to */SLICE_164.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.260 */SLICE_164.B1 to */SLICE_164.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164
ROUTE         1   e 0.001 */SLICE_164.F1 to *SLICE_164.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[5] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_178.CLK to */SLICE_178.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_178.Q0 to */SLICE_178.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]
CTOF_DEL    ---     0.260 */SLICE_178.A1 to */SLICE_178.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178
ROUTE         1   e 0.001 */SLICE_178.F1 to *SLICE_178.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[9] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_174.CLK to */SLICE_174.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174 (from jtaghub16_jtck)
ROUTE         4   e 0.280 */SLICE_174.Q0 to */SLICE_174.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.260 */SLICE_174.A1 to */SLICE_174.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174
ROUTE         1   e 0.001 */SLICE_174.F1 to *SLICE_174.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[1] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_176.CLK to */SLICE_176.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_176.Q0 to */SLICE_176.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.260 */SLICE_176.A1 to */SLICE_176.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176
ROUTE         1   e 0.001 */SLICE_176.F1 to *SLICE_176.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[5] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_47 to mg5ahub/SLICE_47 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_47.CLK to *b/SLICE_47.Q1 mg5ahub/SLICE_47 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_47.Q1 to *b/SLICE_47.C1 mg5ahub/rom_rd_addr_0
CTOF_DEL    ---     0.260 *b/SLICE_47.C1 to *b/SLICE_47.F1 mg5ahub/SLICE_47
ROUTE         1   e 0.001 *b/SLICE_47.F1 to */SLICE_47.DI1 mg5ahub/rom_rd_addr_s_0 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_51 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q1 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q1 to *b/SLICE_51.C1 mg5ahub/rom_rd_addr_2
CTOF_DEL    ---     0.260 *b/SLICE_51.C1 to *b/SLICE_51.F1 mg5ahub/SLICE_51
ROUTE         1   e 0.001 *b/SLICE_51.F1 to */SLICE_51.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_314.CLK to */SLICE_314.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314 (from jtaghub16_jtck)
ROUTE         6   e 0.280 */SLICE_314.Q0 to */SLICE_314.B0 top_reveal_coretop_instance/top_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.260 */SLICE_314.B0 to */SLICE_314.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_49 to mg5ahub/SLICE_49 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_49.CLK to *b/SLICE_49.Q1 mg5ahub/SLICE_49 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_49.Q1 to *b/SLICE_49.C1 mg5ahub/rom_rd_addr_6
CTOF_DEL    ---     0.260 *b/SLICE_49.C1 to *b/SLICE_49.F1 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F1 to */SLICE_49.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_166.CLK to */SLICE_166.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_166.Q0 to */SLICE_166.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]
CTOF_DEL    ---     0.260 */SLICE_166.B1 to */SLICE_166.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166
ROUTE         1   e 0.001 */SLICE_166.F1 to *SLICE_166.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[9] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_124.CLK to */SLICE_124.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_124.Q0 to */SLICE_124.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker
CTOF_DEL    ---     0.260 */SLICE_124.D0 to */SLICE_124.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_180.CLK to */SLICE_180.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_180.Q0 to */SLICE_180.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]
CTOF_DEL    ---     0.260 */SLICE_180.A1 to */SLICE_180.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180
ROUTE         1   e 0.001 */SLICE_180.F1 to *SLICE_180.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[13] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_161.CLK to */SLICE_161.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE         3   e 0.280 */SLICE_161.Q0 to */SLICE_161.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.260 */SLICE_161.B0 to */SLICE_161.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_162.CLK to */SLICE_162.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         4   e 0.280 */SLICE_162.Q0 to */SLICE_162.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.260 */SLICE_162.B1 to */SLICE_162.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F1 to *SLICE_162.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[1] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_72 to mg5ahub/SLICE_72 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_72.CLK to *b/SLICE_72.Q0 mg5ahub/SLICE_72 (from jtaghub16_jtck)
ROUTE         4   e 0.280 *b/SLICE_72.Q0 to *b/SLICE_72.B0 mg5ahub/bit_count_2
CTOF_DEL    ---     0.260 *b/SLICE_72.B0 to *b/SLICE_72.F0 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F0 to */SLICE_72.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_31.CLK to *u/SLICE_31.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31 (from jtaghub16_jtck)
ROUTE         4   e 0.280 *u/SLICE_31.Q0 to *u/SLICE_31.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.260 *u/SLICE_31.B0 to *u/SLICE_31.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31
ROUTE         1   e 0.001 *u/SLICE_31.F0 to */SLICE_31.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_50 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q1 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_50.Q1 to *b/SLICE_50.C1 mg5ahub/rom_rd_addr_4
CTOF_DEL    ---     0.260 *b/SLICE_50.C1 to *b/SLICE_50.F1 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F1 to */SLICE_50.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_32.Q0 to *u/SLICE_32.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.260 *u/SLICE_32.B0 to *u/SLICE_32.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F0 to */SLICE_32.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_71 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q0 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         6   e 0.280 *b/SLICE_71.Q0 to *b/SLICE_71.A0 mg5ahub/bit_count_0
CTOF_DEL    ---     0.260 *b/SLICE_71.A0 to *b/SLICE_71.F0 mg5ahub/SLICE_71
ROUTE         1   e 0.001 *b/SLICE_71.F0 to */SLICE_71.DI0 mg5ahub/bit_count_3_iv_0_m4_0 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q0 to *u/SLICE_33.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.260 *u/SLICE_33.B0 to *u/SLICE_33.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F0 to */SLICE_33.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_71 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q1 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         5   e 0.280 *b/SLICE_71.Q1 to *b/SLICE_71.B1 mg5ahub/bit_count_1
CTOF_DEL    ---     0.260 *b/SLICE_71.B1 to *b/SLICE_71.F1 mg5ahub/SLICE_71
ROUTE         1   e 0.001 *b/SLICE_71.F1 to */SLICE_71.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_175.CLK to */SLICE_175.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_175.Q0 to */SLICE_175.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]
CTOF_DEL    ---     0.260 */SLICE_175.A1 to */SLICE_175.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175
ROUTE         1   e 0.001 */SLICE_175.F1 to *SLICE_175.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[3] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_72 to mg5ahub/SLICE_72 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_72.CLK to *b/SLICE_72.Q1 mg5ahub/SLICE_72 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_72.Q1 to *b/SLICE_72.A1 mg5ahub/bit_count_4
CTOF_DEL    ---     0.260 *b/SLICE_72.A1 to *b/SLICE_72.F1 mg5ahub/SLICE_72
ROUTE         1   e 0.001 *b/SLICE_72.F1 to */SLICE_72.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_51 to mg5ahub/SLICE_51 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_51.CLK to *b/SLICE_51.Q0 mg5ahub/SLICE_51 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_51.Q0 to *b/SLICE_51.C0 mg5ahub/rom_rd_addr_1
CTOF_DEL    ---     0.260 *b/SLICE_51.C0 to *b/SLICE_51.F0 mg5ahub/SLICE_51
ROUTE         1   e 0.001 *b/SLICE_51.F0 to */SLICE_51.DI0 mg5ahub/rom_rd_addr_s_1 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_50 to mg5ahub/SLICE_50 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_50.CLK to *b/SLICE_50.Q0 mg5ahub/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *b/SLICE_50.Q0 to *b/SLICE_50.C0 mg5ahub/rom_rd_addr_3
CTOF_DEL    ---     0.260 *b/SLICE_50.C0 to *b/SLICE_50.F0 mg5ahub/SLICE_50
ROUTE         1   e 0.001 *b/SLICE_50.F0 to */SLICE_50.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_49 to mg5ahub/SLICE_49 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_49.CLK to *b/SLICE_49.Q0 mg5ahub/SLICE_49 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_49.Q0 to *b/SLICE_49.C0 mg5ahub/rom_rd_addr_5
CTOF_DEL    ---     0.260 *b/SLICE_49.C0 to *b/SLICE_49.F0 mg5ahub/SLICE_49
ROUTE         1   e 0.001 *b/SLICE_49.F0 to */SLICE_49.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_32.CLK to *u/SLICE_32.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32 (from jtaghub16_jtck)
ROUTE         4   e 0.280 *u/SLICE_32.Q1 to *u/SLICE_32.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.260 *u/SLICE_32.B1 to *u/SLICE_32.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32
ROUTE         1   e 0.001 *u/SLICE_32.F1 to */SLICE_32.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_33.CLK to *u/SLICE_33.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_33.Q1 to *u/SLICE_33.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.260 *u/SLICE_33.B1 to *u/SLICE_33.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33
ROUTE         1   e 0.001 *u/SLICE_33.F1 to */SLICE_33.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_304.CLK to */SLICE_304.Q0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304 (from jtaghub16_jtck)
ROUTE         6   e 0.280 */SLICE_304.Q0 to */SLICE_304.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.260 */SLICE_304.C0 to */SLICE_304.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304
ROUTE         2   e 0.001 */SLICE_304.F0 to *SLICE_304.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_183.CLK to */SLICE_183.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_183.Q0 to */SLICE_183.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.260 */SLICE_183.C0 to */SLICE_183.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183
ROUTE         1   e 0.001 */SLICE_183.F0 to *SLICE_183.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_71 to mg5ahub/SLICE_71 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_71.CLK to *b/SLICE_71.Q0 mg5ahub/SLICE_71 (from jtaghub16_jtck)
ROUTE         6   e 0.280 *b/SLICE_71.Q0 to *b/SLICE_71.A1 mg5ahub/bit_count_0
CTOF_DEL    ---     0.260 *b/SLICE_71.A1 to *b/SLICE_71.F1 mg5ahub/SLICE_71
ROUTE         1   e 0.001 *b/SLICE_71.F1 to */SLICE_71.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_169.CLK to */SLICE_169.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_169.Q0 to */SLICE_169.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]
CTOF_DEL    ---     0.260 */SLICE_169.B1 to */SLICE_169.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169
ROUTE         1   e 0.001 */SLICE_169.F1 to *SLICE_169.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[15] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_167.CLK to */SLICE_167.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_167.Q0 to */SLICE_167.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]
CTOF_DEL    ---     0.260 */SLICE_167.B1 to */SLICE_167.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167
ROUTE         1   e 0.001 */SLICE_167.F1 to *SLICE_167.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[11] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_165.CLK to */SLICE_165.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_165.Q0 to */SLICE_165.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]
CTOF_DEL    ---     0.260 */SLICE_165.B1 to */SLICE_165.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165
ROUTE         1   e 0.001 */SLICE_165.F1 to *SLICE_165.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[7] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_163.CLK to */SLICE_163.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_163.Q0 to */SLICE_163.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]
CTOF_DEL    ---     0.260 */SLICE_163.B1 to */SLICE_163.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F1 to *SLICE_163.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[3] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_181.CLK to */SLICE_181.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_181.Q0 to */SLICE_181.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]
CTOF_DEL    ---     0.260 */SLICE_181.A1 to */SLICE_181.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181
ROUTE         1   e 0.001 */SLICE_181.F1 to *SLICE_181.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[15] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_179.CLK to */SLICE_179.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_179.Q0 to */SLICE_179.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]
CTOF_DEL    ---     0.260 */SLICE_179.A1 to */SLICE_179.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179
ROUTE         1   e 0.001 */SLICE_179.F1 to *SLICE_179.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[11] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_177.CLK to */SLICE_177.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_177.Q0 to */SLICE_177.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]
CTOF_DEL    ---     0.260 */SLICE_177.A1 to */SLICE_177.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177
ROUTE         1   e 0.001 */SLICE_177.F1 to *SLICE_177.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[7] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_34.CLK to *u/SLICE_34.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *u/SLICE_34.Q1 to *u/SLICE_34.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.260 *u/SLICE_34.B1 to *u/SLICE_34.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34
ROUTE         1   e 0.001 *u/SLICE_34.F1 to */SLICE_34.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[0] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_130.CLK to */SLICE_130.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_130.Q0 to */SLICE_130.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]
CTOF_DEL    ---     0.260 */SLICE_130.D0 to */SLICE_130.F0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35] (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.017ns delay mg5ahub/SLICE_48 to mg5ahub/SLICE_48 (0.924ns delay and 0.093ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_48.CLK to *b/SLICE_48.Q0 mg5ahub/SLICE_48 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_48.Q0 to *b/SLICE_48.C0 mg5ahub/rom_rd_addr_7
CTOF_DEL    ---     0.260 *b/SLICE_48.C0 to *b/SLICE_48.F0 mg5ahub/SLICE_48
ROUTE         1   e 0.001 *b/SLICE_48.F0 to */SLICE_48.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    0.924   (69.6% logic, 30.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_82 to mg5ahub/SLICE_82 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_82.CLK to *b/SLICE_82.Q1 mg5ahub/SLICE_82 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_82.Q1 to *b/SLICE_82.M0 mg5ahub/er1_shift_reg_18 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_109.CLK to */SLICE_109.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_109.Q0 to */SLICE_109.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_115.CLK to */SLICE_115.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115 (from jtaghub16_jtck)
ROUTE        54   e 0.280 */SLICE_115.Q1 to */SLICE_115.M0 top_reveal_coretop_instance/top_la0_inst_0/jshift_d1 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_119.CLK to */SLICE_119.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_119.Q0 to */SLICE_119.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_94.CLK to *u/SLICE_94.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94 (from jtaghub16_jtck)
ROUTE        36   e 0.280 *u/SLICE_94.Q1 to *u/SLICE_94.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[1] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_99.CLK to *u/SLICE_99.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE        24   e 0.280 *u/SLICE_99.Q1 to *u/SLICE_99.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_97.CLK to *u/SLICE_97.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE        19   e 0.280 *u/SLICE_97.Q1 to *u/SLICE_97.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[9] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_96.CLK to *u/SLICE_96.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *u/SLICE_96.Q1 to *u/SLICE_96.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[5] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_83 to mg5ahub/SLICE_83 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_83.CLK to *b/SLICE_83.Q1 mg5ahub/SLICE_83 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_83.Q1 to *b/SLICE_83.M0 mg5ahub/er1_shift_reg_20 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_76 to mg5ahub/SLICE_76 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_76.CLK to *b/SLICE_76.Q1 mg5ahub/SLICE_76 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_76.Q1 to *b/SLICE_76.M0 mg5ahub/er1_shift_reg_6 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_78 to mg5ahub/SLICE_78 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_78.CLK to *b/SLICE_78.Q1 mg5ahub/SLICE_78 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_78.Q1 to *b/SLICE_78.M0 mg5ahub/er1_shift_reg_10 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_80 to mg5ahub/SLICE_80 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_80.CLK to *b/SLICE_80.Q1 mg5ahub/SLICE_80 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_80.Q1 to *b/SLICE_80.M0 mg5ahub/er1_shift_reg_14 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_128.CLK to */SLICE_128.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_128.Q1 to */SLICE_128.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_77 to mg5ahub/SLICE_77 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_77.CLK to *b/SLICE_77.Q1 mg5ahub/SLICE_77 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_77.Q1 to *b/SLICE_77.M0 mg5ahub/er1_shift_reg_8 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_113.CLK to */SLICE_113.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113 (from jtaghub16_jtck)
ROUTE         9   e 0.280 */SLICE_113.Q0 to */SLICE_113.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_118.CLK to */SLICE_118.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_118.Q0 to */SLICE_118.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_120.CLK to */SLICE_120.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120 (from jtaghub16_jtck)
ROUTE         2   e 0.280 */SLICE_120.Q0 to */SLICE_120.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_100.CLK to */SLICE_100.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         5   e 0.280 */SLICE_100.Q1 to */SLICE_100.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[15] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_127.CLK to */SLICE_127.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_127.Q1 to */SLICE_127.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_107.CLK to */SLICE_107.Q0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_107.Q0 to */SLICE_107.M1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_75 to mg5ahub/SLICE_75 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_75.CLK to *b/SLICE_75.Q1 mg5ahub/SLICE_75 (from jtaghub16_jtck)
ROUTE         2   e 0.280 *b/SLICE_75.Q1 to *b/SLICE_75.M0 mg5ahub/er1_shift_reg_4 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_98.CLK to *u/SLICE_98.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         3   e 0.280 *u/SLICE_98.Q1 to *u/SLICE_98.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[11] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 *SLICE_212.CLK to */SLICE_212.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212 (from jtaghub16_jtck)
ROUTE         1   e 0.280 */SLICE_212.Q0 to */SLICE_212.M1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_79 to mg5ahub/SLICE_79 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_79.CLK to *b/SLICE_79.Q1 mg5ahub/SLICE_79 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_79.Q1 to *b/SLICE_79.M0 mg5ahub/er1_shift_reg_12 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_81 to mg5ahub/SLICE_81 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_81.CLK to *b/SLICE_81.Q1 mg5ahub/SLICE_81 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_81.Q1 to *b/SLICE_81.M0 mg5ahub/er1_shift_reg_16 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay mg5ahub/SLICE_74 to mg5ahub/SLICE_74 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_74.CLK to *b/SLICE_74.Q1 mg5ahub/SLICE_74 (from jtaghub16_jtck)
ROUTE         1   e 0.280 *b/SLICE_74.Q1 to *b/SLICE_74.M0 mg5ahub/er1_shift_reg_2 (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.811ns delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (0.663ns delay and 0.148ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383 */SLICE_95.CLK to *u/SLICE_95.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE        16   e 0.280 *u/SLICE_95.Q1 to *u/SLICE_95.M0 top_reveal_coretop_instance/top_la0_inst_0/addr[3] (to jtaghub16_jtck)
                  --------
                    0.663   (57.8% logic, 42.2% route), 1 logic levels.


================================================================================
Preference: Unconstrained: INPUT_SETUP
            0 unconstrained paths found
--------------------------------------------------------------------------------


================================================================================
Preference: Unconstrained: CLOCK_TO_OUT
            1 unconstrained path found
--------------------------------------------------------------------------------

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opUART_Tx" CLKPORT "ipClk" 

Report:    3.647ns delay opUART_Tx_MGIOL to opUART_Tx

   Name    Fanout   Delay (ns)          Site               Resource
C2OUT_DEL   ---     1.603 *_Tx_MGIOL.CLK to *x_MGIOL.IOLDO opUART_Tx_MGIOL (from ipClk_c)
ROUTE         1   e 1.081 *x_MGIOL.IOLDO to      109.IOLDO opUART_Tx_c
DOPAD_DEL   ---     0.963      109.IOLDO to        109.PAD opUART_Tx
                  --------
                    3.647   (70.4% logic, 29.6% route), 2 logic levels.


================================================================================
Preference: Unconstrained: MAXDELAY
            0 unconstrained paths found
--------------------------------------------------------------------------------

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "ipClk" 50.000000 MHz ;  |   50.000 MHz|  105.831 MHz|   7  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 289 clocks:

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_end_i   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449.F1   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[46]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[45]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[44]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[43]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[42]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[41]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[40]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[39]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[38]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[37]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[36]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[31]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[30]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[29]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[28]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[27]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[26]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[25]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[24]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[21]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[20]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[19]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[18]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[17]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[16]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_424.F0   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_211.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_211.Q0   Loads: 7
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/SLICE_553.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/parity_err   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184.Q0   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_345.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.F0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113.Q1   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.F1   Loads: 17
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113.Q0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_541.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395.F0   Loads: 29
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jshift_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115.Q1   Loads: 54
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/capture_dr   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.F0   Loads: 14
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr_15   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_424.Q0   Loads: 21
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97.Q1   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97.Q0   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96.Q0   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95.Q1   Loads: 16
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95.Q0   Loads: 31
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94.Q1   Loads: 36
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99.Q1   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99.Q0   Loads: 20
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94.Q0   Loads: 39
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_7   Source: mg5ahub/SLICE_48.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_6   Source: mg5ahub/SLICE_49.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_5   Source: mg5ahub/SLICE_49.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_4   Source: mg5ahub/SLICE_50.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_3   Source: mg5ahub/SLICE_50.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_2   Source: mg5ahub/SLICE_51.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_1   Source: mg5ahub/SLICE_51.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_0   Source: mg5ahub/SLICE_47.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/jce1   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/id_enable_0_sqmuxa   Source: mg5ahub/SLICE_568.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_9   Source: mg5ahub/SLICE_78.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_8   Source: mg5ahub/SLICE_77.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_7   Source: mg5ahub/SLICE_77.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_6   Source: mg5ahub/SLICE_76.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_5   Source: mg5ahub/SLICE_76.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_4   Source: mg5ahub/SLICE_75.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_3   Source: mg5ahub/SLICE_75.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_20   Source: mg5ahub/SLICE_83.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_2   Source: mg5ahub/SLICE_74.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_19   Source: mg5ahub/SLICE_83.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_18   Source: mg5ahub/SLICE_82.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_17   Source: mg5ahub/SLICE_82.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_16   Source: mg5ahub/SLICE_81.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_15   Source: mg5ahub/SLICE_81.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_14   Source: mg5ahub/SLICE_80.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_13   Source: mg5ahub/SLICE_80.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_12   Source: mg5ahub/SLICE_79.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_11   Source: mg5ahub/SLICE_79.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_10   Source: mg5ahub/SLICE_78.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/bit_count_3_iv_0_m4_0   Source: mg5ahub/SLICE_71.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_49_i   Source: mg5ahub/SLICE_71.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_48_i   Source: mg5ahub/SLICE_72.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_47_i   Source: mg5ahub/SLICE_73.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_46_i   Source: mg5ahub/SLICE_72.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_45_i   Source: mg5ahub/SLICE_569.F0   Loads: 10
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jupdate   Source: mg5ahub/genblk0_genblk5_jtage_u.JUPDATE   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtdi   Source: mg5ahub/genblk0_genblk5_jtage_u.JTDI   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK   Loads: 169
   No transfer within this clock domain is found

Clock Domain: jtaghub16_jshift   Source: mg5ahub/genblk0_genblk5_jtage_u.JSHIFT   Loads: 54
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jrstn   Source: mg5ahub/genblk0_genblk5_jtage_u.JRSTN   Loads: 167
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jce2   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE2   Loads: 23
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_ip_enable0   Source: SLICE_572.Q0   Loads: 53
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: ipClk_c   Source: ipClk.PAD   Loads: 148
   Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ;

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK


--------------------------------------------------------------------------------
                Connections not covered by the preferences
--------------------------------------------------------------------------------

     Delay                        Element                 Net

  e 1.081ns          ipClk.PADDI to _int_u/SLICE_110.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to _int_u/SLICE_121.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_189.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_195.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_198.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_208.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_217.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_218.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_219.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_220.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_221.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_222.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_223.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_224.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_225.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_226.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_227.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_228.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_229.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_230.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_231.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_232.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_233.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_234.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_235.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_236.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_237.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_239.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to u/te_0/SLICE_282.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to u/te_0/SLICE_300.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to u/te_0/SLICE_301.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to u/tu_0/SLICE_308.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to u/tu_0/SLICE_312.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to 0/tm_u/SLICE_428.CLK ipClk_c
  e 1.081ns          ipClk.PADDI to p12e1ac7f_0_0_0.CLKA ipClk_c
  e 1.081ns          ipClk.PADDI to p12e1ac7f_0_0_0.CLKB ipClk_c
  e 1.081ns          ipClk.PADDI to p12e1ac7f_0_0_0.CLKB ipClk_c
  e 1.081ns          ipClk.PADDI to p132a0a97_0_1_0.CLKW ipClk_c
  e 1.081ns          ipClk.PADDI to p132a0a97_0_0_1.CLKW ipClk_c
  e 1.081ns pUART_Tx_MGIOL.IOLDO to      opUART_Tx.IOLDO opUART_Tx_c
  e 1.081ns _u/tu_0/SLICE_310.Q0 to /trig_u/SLICE_366.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]
  e 1.081ns _u/tu_0/SLICE_310.Q1 to _u/tu_0/SLICE_478.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]
  e 0.280ns _u/tu_0/SLICE_479.Q0 to _u/tu_0/SLICE_479.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]
  e 0.280ns /trig_u/SLICE_366.Q0 to /trig_u/SLICE_366.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]
  e 0.280ns /trig_u/SLICE_366.F0 to /trig_u/SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
  e 1.081ns _u/tu_0/SLICE_478.F0 to /trig_u/SLICE_363.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][1]
  e 1.081ns _u/tu_0/SLICE_479.F0 to /trig_u/SLICE_364.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][2]
  e 1.081ns 93[1]/SLICE_327.OFX0 to _inst_0/SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
  e 1.081ns _u/te_0/SLICE_280.Q0 to 8S93[1]/SLICE_327.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
  e 1.081ns _u/te_0/SLICE_280.Q0 to 8S93[1]/SLICE_327.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
  e 1.081ns _u/te_0/SLICE_283.Q0 to 8S93[1]/SLICE_327.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
  e 1.081ns _u/te_0/SLICE_281.Q0 to 8S93[1]/SLICE_327.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]
  e 1.081ns _u/te_0/SLICE_369.F1 to _u/te_0/SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0
  e 1.081ns _u/te_0/SLICE_292.Q0 to _u/te_0/SLICE_284.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]
  e 0.001ns _u/te_0/SLICE_284.F0 to u/te_0/SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0]
  e 1.081ns _u/te_0/SLICE_292.Q1 to _u/te_0/SLICE_284.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]
  e 0.001ns _u/te_0/SLICE_284.F1 to u/te_0/SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1]
  e 0.001ns _u/te_0/SLICE_285.F0 to u/te_0/SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2]
  e 1.081ns _u/te_0/SLICE_293.Q0 to _u/te_0/SLICE_285.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]
  e 0.001ns _u/te_0/SLICE_285.F1 to u/te_0/SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3]
  e 1.081ns _u/te_0/SLICE_293.Q1 to _u/te_0/SLICE_285.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]
  e 0.001ns _u/te_0/SLICE_286.F0 to u/te_0/SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4]
  e 1.081ns _u/te_0/SLICE_294.Q0 to _u/te_0/SLICE_286.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]
  e 0.001ns _u/te_0/SLICE_286.F1 to u/te_0/SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5]
  e 1.081ns _u/te_0/SLICE_294.Q1 to _u/te_0/SLICE_286.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]
  e 1.081ns _u/te_0/SLICE_295.Q0 to _u/te_0/SLICE_287.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]
  e 0.001ns _u/te_0/SLICE_287.F0 to u/te_0/SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6]
  e 1.081ns _u/te_0/SLICE_295.Q1 to _u/te_0/SLICE_287.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]
  e 0.001ns _u/te_0/SLICE_287.F1 to u/te_0/SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7]
  e 0.001ns _u/te_0/SLICE_288.F0 to u/te_0/SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8]
  e 1.081ns _u/te_0/SLICE_296.Q0 to _u/te_0/SLICE_288.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]
  e 1.081ns _u/te_0/SLICE_296.Q1 to _u/te_0/SLICE_288.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]
  e 0.001ns _u/te_0/SLICE_288.F1 to u/te_0/SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9]
  e 1.081ns _u/te_0/SLICE_297.Q0 to _u/te_0/SLICE_289.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]
  e 0.001ns _u/te_0/SLICE_289.F0 to u/te_0/SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10]
  e 0.001ns _u/te_0/SLICE_289.F1 to u/te_0/SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11]
  e 1.081ns _u/te_0/SLICE_297.Q1 to _u/te_0/SLICE_289.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]
  e 1.081ns _u/te_0/SLICE_298.Q0 to _u/te_0/SLICE_290.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]
  e 0.001ns _u/te_0/SLICE_290.F0 to u/te_0/SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12]
  e 1.081ns _u/te_0/SLICE_298.Q1 to _u/te_0/SLICE_290.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]
  e 0.001ns _u/te_0/SLICE_290.F1 to u/te_0/SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13]
  e 0.001ns _u/te_0/SLICE_291.F0 to u/te_0/SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14]
  e 1.081ns _u/te_0/SLICE_299.Q0 to _u/te_0/SLICE_291.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]
  e 1.081ns _u/te_0/SLICE_299.Q1 to _u/te_0/SLICE_291.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]
  e 0.001ns _u/te_0/SLICE_291.F1 to u/te_0/SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15]
  e 0.280ns _u/te_0/SLICE_369.F0 to _u/te_0/SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
  e 1.081ns _u/te_0/SLICE_370.F1 to _u/te_0/SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
  e 1.081ns /tcnt_0/SLICE_371.Q0 to /tcnt_0/SLICE_372.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]
  e 1.081ns /tcnt_0/SLICE_274.Q0 to /tcnt_0/SLICE_372.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]
  e 1.081ns /tcnt_0/SLICE_274.Q1 to /tcnt_0/SLICE_489.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]
  e 0.280ns /tcnt_0/SLICE_487.Q0 to /tcnt_0/SLICE_487.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]
  e 0.280ns /tcnt_0/SLICE_372.Q0 to /tcnt_0/SLICE_372.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]
  e 1.081ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_184.A0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 1.081ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_407.A1 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 1.081ns _inst_0/SLICE_549.Q0 to /tcnt_0/SLICE_487.C0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 1.081ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_548.A0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.280ns _inst_0/SLICE_549.Q0 to _inst_0/SLICE_549.B0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 1.081ns /tcnt_0/SLICE_272.Q0 to _inst_0/SLICE_460.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]
  e 0.280ns /tcnt_0/SLICE_372.F1 to /tcnt_0/SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
  e 1.081ns /tcnt_0/SLICE_372.F0 to /trig_u/SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
  e 1.081ns /tcnt_0/SLICE_487.F0 to /trig_u/SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
  e 1.081ns /tcnt_0/SLICE_489.F0 to /trig_u/SLICE_363.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[1]
  e 1.081ns /trig_u/SLICE_366.F1 to _inst_0/SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
  e 0.280ns _inst_0/SLICE_374.F0 to _inst_0/SLICE_374.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 1.081ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 1.081ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 1.081ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_410.C0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 1.081ns /trig_u/SLICE_364.F1 to g_int_u/SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
  e 1.081ns /trig_u/SLICE_363.F1 to g_int_u/SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
  e 1.081ns _inst_0/SLICE_460.F1 to g_int_u/SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
  e 1.081ns g_int_u/SLICE_548.F0 to c_RNO_2/SLICE_328.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_o3_0_1
  e 1.081ns RNO_2/SLICE_328.OFX0 to g_int_u/SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
  e 1.081ns g_int_u/SLICE_404.F1 to c_RNO_2/SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
  e 1.081ns _inst_0/SLICE_374.F1 to c_RNO_2/SLICE_328.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_25
  e 0.001ns g_int_u/SLICE_162.F0 to _int_u/SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0]
  e 0.001ns g_int_u/SLICE_315.F0 to _int_u/SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i
  e 0.001ns g_int_u/SLICE_315.F1 to _int_u/SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i
  e 0.001ns g_int_u/SLICE_316.F0 to _int_u/SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i
  e 0.001ns g_int_u/SLICE_316.F1 to _int_u/SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i
  e 0.001ns g_int_u/SLICE_317.F0 to _int_u/SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i
  e 0.001ns g_int_u/SLICE_317.F1 to _int_u/SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i
  e 0.001ns int_u/SLICE_318.OFX0 to _int_u/SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6]
  e 0.001ns g_int_u/SLICE_319.F0 to _int_u/SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i
  e 0.001ns g_int_u/SLICE_320.F0 to _int_u/SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i
  e 0.001ns g_int_u/SLICE_320.F1 to _int_u/SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i
  e 0.001ns int_u/SLICE_321.OFX0 to _int_u/SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57
  e 0.001ns g_int_u/SLICE_322.F0 to _int_u/SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i
  e 0.001ns g_int_u/SLICE_322.F1 to _int_u/SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i
  e 0.001ns g_int_u/SLICE_184.F0 to _int_u/SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3
  e 0.001ns g_int_u/SLICE_123.F0 to _int_u/SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5
  e 1.081ns g_int_u/SLICE_122.Q0 to g_int_u/SLICE_112.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]
  e 1.081ns g_int_u/SLICE_122.Q1 to g_int_u/SLICE_112.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]
  e 0.280ns g_int_u/SLICE_112.F1 to g_int_u/SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i
  e 1.081ns g_int_u/SLICE_379.F0 to g_int_u/SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
  e 1.081ns g_int_u/SLICE_380.F0 to g_int_u/SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
  e 1.081ns g_int_u/SLICE_381.F0 to g_int_u/SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
  e 1.081ns g_int_u/SLICE_384.F0 to g_int_u/SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
  e 1.081ns g_int_u/SLICE_385.F0 to g_int_u/SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
  e 1.081ns g_int_u/SLICE_386.F0 to g_int_u/SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
  e 1.081ns g_int_u/SLICE_387.F0 to g_int_u/SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
  e 1.081ns g_int_u/SLICE_388.F0 to g_int_u/SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
  e 1.081ns g_int_u/SLICE_389.F0 to g_int_u/SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
  e 1.081ns g_int_u/SLICE_390.F0 to g_int_u/SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
  e 1.081ns g_int_u/SLICE_391.F0 to g_int_u/SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
  e 1.081ns g_int_u/SLICE_536.F0 to g_int_u/SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
  e 1.081ns g_int_u/SLICE_537.F0 to g_int_u/SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
  e 1.081ns g_int_u/SLICE_394.F0 to g_int_u/SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
  e 0.280ns g_int_u/SLICE_380.F1 to g_int_u/SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
  e 0.280ns g_int_u/SLICE_381.F1 to g_int_u/SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
  e 0.280ns g_int_u/SLICE_384.F1 to g_int_u/SLICE_384.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[3]
  e 0.280ns g_int_u/SLICE_385.F1 to g_int_u/SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
  e 0.280ns g_int_u/SLICE_386.F1 to g_int_u/SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
  e 0.280ns g_int_u/SLICE_387.F1 to g_int_u/SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
  e 0.280ns g_int_u/SLICE_388.F1 to g_int_u/SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
  e 0.280ns g_int_u/SLICE_389.F1 to g_int_u/SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
  e 0.280ns g_int_u/SLICE_390.F1 to g_int_u/SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
  e 0.280ns g_int_u/SLICE_391.F1 to g_int_u/SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
  e 1.081ns g_int_u/SLICE_461.F1 to g_int_u/SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
  e 1.081ns g_int_u/SLICE_461.F0 to g_int_u/SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
  e 1.081ns _inst_0/SLICE_460.F0 to g_int_u/SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
  e 1.081ns _0/tm_u/SLICE_187.Q0 to g_int_u/SLICE_384.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[4]
  e 1.081ns _0/tm_u/SLICE_185.Q1 to g_int_u/SLICE_461.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[1]
  e 1.081ns _0/tm_u/SLICE_186.Q0 to g_int_u/SLICE_461.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[2]
  e 1.081ns _0/tm_u/SLICE_186.Q1 to _inst_0/SLICE_460.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[3]
  e 1.081ns _0/tm_u/SLICE_187.Q1 to g_int_u/SLICE_385.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
  e 1.081ns _0/tm_u/SLICE_187.Q1 to g_int_u/SLICE_387.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
  e 1.081ns _0/tm_u/SLICE_188.Q0 to g_int_u/SLICE_386.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[6]
  e 1.081ns _0/tm_u/SLICE_188.Q1 to g_int_u/SLICE_536.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[7]
  e 1.081ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_388.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 1.081ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_390.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 1.081ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_391.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 1.081ns _0/tm_u/SLICE_189.Q1 to g_int_u/SLICE_389.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
  e 1.081ns _0/tm_u/SLICE_189.Q1 to g_int_u/SLICE_537.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
  e 1.081ns g_int_u/SLICE_405.F0 to g_int_u/SLICE_376.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/rd_dout_tm_m_1[0]
  e 1.081ns g_int_u/SLICE_376.F1 to g_int_u/SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
  e 1.081ns g_int_u/SLICE_402.F1 to g_int_u/SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
  e 1.081ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_349.B1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 1.081ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_405.C0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 1.081ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_456.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 1.081ns g_int_u/SLICE_407.F1 to g_int_u/SLICE_406.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
  e 1.081ns g_int_u/SLICE_407.F1 to g_int_u/SLICE_414.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
  e 1.081ns g_int_u/SLICE_456.F1 to g_int_u/SLICE_403.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_115_0
  e 1.081ns _inst_0/SLICE_549.F0 to g_int_u/SLICE_410.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_o4_1_0
  e 1.081ns g_int_u/SLICE_410.F0 to g_int_u/SLICE_123.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_o4_1_2
  e 1.081ns g_int_u/SLICE_349.F0 to g_int_u/SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
  e 1.081ns g_int_u/SLICE_403.F1 to g_int_u/SLICE_409.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1_1
  e 1.081ns g_int_u/SLICE_409.F1 to g_int_u/SLICE_123.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1
  e 1.081ns g_int_u/SLICE_411.F1 to g_int_u/SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
  e 0.280ns g_int_u/SLICE_123.F1 to g_int_u/SLICE_123.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_1
  e 1.081ns g_int_u/SLICE_406.F1 to g_int_u/SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
  e 0.280ns g_int_u/SLICE_349.F1 to g_int_u/SLICE_349.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_36
  e 1.081ns g_int_u/SLICE_414.F0 to g_int_u/SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5

--------------------------------------------------------------------------------


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 5179 paths, 1 nets, and 3574 connections (94.90% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Fri Apr 29 17:40:24 2022

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -c -u 0 -gt -mapchkpnt 0 -sethld -o Counter_impl1.tw1 -gui -msgset C:/Users/Dayalan Nair/Desktop/UCT-FPGA-Course-2022/dnair_practicals/Counter/promote.xml Counter_impl1_map.ncd Counter_impl1.prf 
Design file:     counter_impl1_map.ncd
Preference file: counter_impl1.prf
Device,speed:    LFXP2-5E,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

Preference Summary


  • FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
    •             4096 items scored, 0 timing errors detected.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
    •             1 item scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" (0 errors)
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  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" (0 errors)
    •             0 items scored.


  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" (0 errors)
    •             0 items scored.

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ;
            4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.237ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              UART_Inst/opRxData[6]  (from ipClk_c +)
   Destination:    FF         Data in        UART_Inst/opRxData[5]  (to ipClk_c +)

   Delay:               0.223ns  (53.8% logic, 46.2% route), 1 logic levels.

 Constraint Details:

      0.223ns physical path delay UART_Inst/SLICE_62 to UART_Inst/SLICE_62 meets
     -0.014ns M_HLD and
      0.000ns delay constraint requirement (totaling -0.014ns) by 0.237ns

 Physical Path Details:

      Data path UART_Inst/SLICE_62 to UART_Inst/SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.120 */SLICE_62.CLK to *t/SLICE_62.Q1 UART_Inst/SLICE_62 (from ipClk_c)
ROUTE         9   e 0.103 *t/SLICE_62.Q1 to *t/SLICE_62.M0 UART_RxData[6] (to ipClk_c)
                  --------
                    0.223   (53.8% logic, 46.2% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipnReset
   Destination:    FF         Data in        UART_Inst/rst  (to ipClk_c +)

   Delay:               0.867ns  (48.0% logic, 52.0% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557         19.PAD to       19.PADDI ipnReset
ROUTE         1   e 0.450       19.PADDI to *t/SLICE_52.A0 ipnReset_c
CTOF_DEL    ---     0.085 *t/SLICE_52.A0 to *t/SLICE_52.F0 UART_Inst/SLICE_52
ROUTE         1   e 0.001 *t/SLICE_52.F0 to */SLICE_52.DI0 UART_Inst/ipnReset_c_i (to ipClk_c)
                  --------
                    1.093   (58.7% logic, 41.3% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        UART_Inst_rxio  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 0.450      110.PADDI to *T_Rx_MGIOL.DI ipUART_Rx_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 0.450      110.PADDI to */SLICE_216.M0 ipUART_Rx_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipUART_Rx
   Destination:    FF         Data in        top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557        110.PAD to      110.PADDI ipUART_Rx
ROUTE         3   e 0.450      110.PADDI to */SLICE_238.M1 ipUART_Rx_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" ;
            0 items scored.
--------------------------------------------------------------------------------

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "ipClk" 50.000000 MHz ;  |            -|            -|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 289 clocks:

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/un1_tt_end_1_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_368.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_304.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_369.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_367.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_end_i   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_314.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnte   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_449.F1   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_288.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_287.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_286.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_285.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_291.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_290.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_289.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_284.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_94_i   Source: top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_302.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[46]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[45]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[44]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[43]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[42]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[41]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[40]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[39]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[38]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[37]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[36]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[31]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[30]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[29]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[28]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[27]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[26]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[25]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[24]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[21]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[20]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[19]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[18]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOB0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[17]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[16]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_424.F0   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_211.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_214.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_213.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_212.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_211.Q0   Loads: 7
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/SLICE_553.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/tm_u/N_437_i   Source: top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_215.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/parity_err   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184.Q0   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_4_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_344.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un1_jtdo_1_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_392.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en_3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_183.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr_5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_182.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_178.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_177.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_176.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_175.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_181.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_180.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_179.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_7[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_174.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_173.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_172.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_171.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_437.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_166.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[7]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_165.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_164.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_163.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_169.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_168.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_167.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_162.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block_3_iv_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_161.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_160.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_159.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_158.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_157.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_156.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_155.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_154.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_153.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_152.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_138.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_151.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_150.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_149.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_148.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_147.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_146.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_145.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_142.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_318.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_130.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_345.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_128.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_127.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_539.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_184.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker_4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_124.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_123.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_int   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.F0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_120.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_119.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113.Q1   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1_RNITJK61   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.F1   Loads: 17
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_113.Q0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_112.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_541.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_109.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_108.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_31.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_32.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_33.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt_s[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_34.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_118.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_584   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_144.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_321.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_56   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_323.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_536   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_143.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_488   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_472   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_141.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_456   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_440   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_140.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_424   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_408   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_139.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_360   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_137.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_14_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_317.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_319.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1121_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_395.F0   Loads: 29
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1114_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_378.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_315.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_316.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_320.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_322.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/jshift_d1   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_115.Q1   Loads: 54
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/capture_dr   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_107.F0   Loads: 14
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr_15   Source: top_reveal_coretop_instance/top_la0_inst_0/SLICE_424.Q0   Loads: 21
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[9]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97.Q1   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[8]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_97.Q0   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[5]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[4]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_96.Q0   Loads: 11
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[3]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95.Q1   Loads: 16
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[2]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_95.Q0   Loads: 31
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[1]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94.Q1   Loads: 36
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[15]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[14]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_100.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[13]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99.Q1   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[12]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_99.Q0   Loads: 20
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[11]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[10]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_98.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: top_reveal_coretop_instance/top_la0_inst_0/addr[0]   Source: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_94.Q0   Loads: 39
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_7   Source: mg5ahub/SLICE_48.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_6   Source: mg5ahub/SLICE_49.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_5   Source: mg5ahub/SLICE_49.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_4   Source: mg5ahub/SLICE_50.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_3   Source: mg5ahub/SLICE_50.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_2   Source: mg5ahub/SLICE_51.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_1   Source: mg5ahub/SLICE_51.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_0   Source: mg5ahub/SLICE_47.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/jce1   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/id_enable_0_sqmuxa   Source: mg5ahub/SLICE_568.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_9   Source: mg5ahub/SLICE_78.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_8   Source: mg5ahub/SLICE_77.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_7   Source: mg5ahub/SLICE_77.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_6   Source: mg5ahub/SLICE_76.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_5   Source: mg5ahub/SLICE_76.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_4   Source: mg5ahub/SLICE_75.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_3   Source: mg5ahub/SLICE_75.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_20   Source: mg5ahub/SLICE_83.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_2   Source: mg5ahub/SLICE_74.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_19   Source: mg5ahub/SLICE_83.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_18   Source: mg5ahub/SLICE_82.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_17   Source: mg5ahub/SLICE_82.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_16   Source: mg5ahub/SLICE_81.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_15   Source: mg5ahub/SLICE_81.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_14   Source: mg5ahub/SLICE_80.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_13   Source: mg5ahub/SLICE_80.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_12   Source: mg5ahub/SLICE_79.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_11   Source: mg5ahub/SLICE_79.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_10   Source: mg5ahub/SLICE_78.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/bit_count_3_iv_0_m4_0   Source: mg5ahub/SLICE_71.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_49_i   Source: mg5ahub/SLICE_71.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_48_i   Source: mg5ahub/SLICE_72.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_47_i   Source: mg5ahub/SLICE_73.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_46_i   Source: mg5ahub/SLICE_72.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_45_i   Source: mg5ahub/SLICE_569.F0   Loads: 10
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jupdate   Source: mg5ahub/genblk0_genblk5_jtage_u.JUPDATE   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtdi   Source: mg5ahub/genblk0_genblk5_jtage_u.JTDI   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK   Loads: 169
   No transfer within this clock domain is found

Clock Domain: jtaghub16_jshift   Source: mg5ahub/genblk0_genblk5_jtage_u.JSHIFT   Loads: 54
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jrstn   Source: mg5ahub/genblk0_genblk5_jtage_u.JRSTN   Loads: 167
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jce2   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE2   Loads: 23
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_ip_enable0   Source: SLICE_572.Q0   Loads: 53
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: ipClk_c   Source: ipClk.PAD   Loads: 148
   Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ;

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK


--------------------------------------------------------------------------------
                Connections not covered by the preferences
--------------------------------------------------------------------------------

     Delay                        Element                 Net

  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_280.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_283.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_292.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_293.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_294.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_295.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_296.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_297.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_298.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to u/te_0/SLICE_299.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to inst_0/SLICE_549.CLK ipClk_c
  e 0.450ns          ipClk.PADDI to p12e1ac7f_0_0_0.CLKA ipClk_c
  e 0.450ns pUART_Tx_MGIOL.IOLDO to      opUART_Tx.IOLDO opUART_Tx_c
  e 0.450ns _u/tu_0/SLICE_310.Q0 to /trig_u/SLICE_366.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]
  e 0.450ns _u/tu_0/SLICE_310.Q1 to _u/tu_0/SLICE_478.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]
  e 0.103ns _u/tu_0/SLICE_479.Q0 to _u/tu_0/SLICE_479.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]
  e 0.103ns /trig_u/SLICE_366.Q0 to /trig_u/SLICE_366.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]
  e 0.103ns /trig_u/SLICE_366.F0 to /trig_u/SLICE_366.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][0]
  e 0.450ns _u/tu_0/SLICE_478.F0 to /trig_u/SLICE_363.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][1]
  e 0.450ns _u/tu_0/SLICE_479.F0 to /trig_u/SLICE_364.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tu[0][2]
  e 0.450ns 93[1]/SLICE_327.OFX0 to _inst_0/SLICE_374.B0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_te[0][0]
  e 0.450ns _u/te_0/SLICE_280.Q0 to 8S93[1]/SLICE_327.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
  e 0.450ns _u/te_0/SLICE_280.Q0 to 8S93[1]/SLICE_327.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]
  e 0.450ns _u/te_0/SLICE_283.Q0 to 8S93[1]/SLICE_327.D1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
  e 0.450ns _u/te_0/SLICE_281.Q0 to 8S93[1]/SLICE_327.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]
  e 0.450ns _u/te_0/SLICE_369.F1 to _u/te_0/SLICE_304.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0
  e 0.450ns _u/te_0/SLICE_292.Q0 to _u/te_0/SLICE_284.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]
  e 0.001ns _u/te_0/SLICE_284.F0 to u/te_0/SLICE_284.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[0]
  e 0.450ns _u/te_0/SLICE_292.Q1 to _u/te_0/SLICE_284.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]
  e 0.001ns _u/te_0/SLICE_284.F1 to u/te_0/SLICE_284.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[1]
  e 0.001ns _u/te_0/SLICE_285.F0 to u/te_0/SLICE_285.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[2]
  e 0.450ns _u/te_0/SLICE_293.Q0 to _u/te_0/SLICE_285.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]
  e 0.001ns _u/te_0/SLICE_285.F1 to u/te_0/SLICE_285.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[3]
  e 0.450ns _u/te_0/SLICE_293.Q1 to _u/te_0/SLICE_285.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]
  e 0.001ns _u/te_0/SLICE_286.F0 to u/te_0/SLICE_286.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[4]
  e 0.450ns _u/te_0/SLICE_294.Q0 to _u/te_0/SLICE_286.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]
  e 0.001ns _u/te_0/SLICE_286.F1 to u/te_0/SLICE_286.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[5]
  e 0.450ns _u/te_0/SLICE_294.Q1 to _u/te_0/SLICE_286.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]
  e 0.450ns _u/te_0/SLICE_295.Q0 to _u/te_0/SLICE_287.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]
  e 0.001ns _u/te_0/SLICE_287.F0 to u/te_0/SLICE_287.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[6]
  e 0.450ns _u/te_0/SLICE_295.Q1 to _u/te_0/SLICE_287.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]
  e 0.001ns _u/te_0/SLICE_287.F1 to u/te_0/SLICE_287.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[7]
  e 0.001ns _u/te_0/SLICE_288.F0 to u/te_0/SLICE_288.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[8]
  e 0.450ns _u/te_0/SLICE_296.Q0 to _u/te_0/SLICE_288.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]
  e 0.450ns _u/te_0/SLICE_296.Q1 to _u/te_0/SLICE_288.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]
  e 0.001ns _u/te_0/SLICE_288.F1 to u/te_0/SLICE_288.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[9]
  e 0.450ns _u/te_0/SLICE_297.Q0 to _u/te_0/SLICE_289.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]
  e 0.001ns _u/te_0/SLICE_289.F0 to u/te_0/SLICE_289.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[10]
  e 0.001ns _u/te_0/SLICE_289.F1 to u/te_0/SLICE_289.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[11]
  e 0.450ns _u/te_0/SLICE_297.Q1 to _u/te_0/SLICE_289.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]
  e 0.450ns _u/te_0/SLICE_298.Q0 to _u/te_0/SLICE_290.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]
  e 0.001ns _u/te_0/SLICE_290.F0 to u/te_0/SLICE_290.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[12]
  e 0.450ns _u/te_0/SLICE_298.Q1 to _u/te_0/SLICE_290.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]
  e 0.001ns _u/te_0/SLICE_290.F1 to u/te_0/SLICE_290.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[13]
  e 0.001ns _u/te_0/SLICE_291.F0 to u/te_0/SLICE_291.DI0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[14]
  e 0.450ns _u/te_0/SLICE_299.Q0 to _u/te_0/SLICE_291.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]
  e 0.450ns _u/te_0/SLICE_299.Q1 to _u/te_0/SLICE_291.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]
  e 0.001ns _u/te_0/SLICE_291.F1 to u/te_0/SLICE_291.DI1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_lm[15]
  e 0.103ns _u/te_0/SLICE_369.F0 to _u/te_0/SLICE_369.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_97
  e 0.450ns _u/te_0/SLICE_370.F1 to _u/te_0/SLICE_369.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78
  e 0.450ns /tcnt_0/SLICE_371.Q0 to /tcnt_0/SLICE_372.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]
  e 0.450ns /tcnt_0/SLICE_274.Q0 to /tcnt_0/SLICE_372.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]
  e 0.450ns /tcnt_0/SLICE_274.Q1 to /tcnt_0/SLICE_489.C0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]
  e 0.103ns /tcnt_0/SLICE_487.Q0 to /tcnt_0/SLICE_487.D0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]
  e 0.103ns /tcnt_0/SLICE_372.Q0 to /tcnt_0/SLICE_372.B1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]
  e 0.450ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_184.A0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.450ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_407.A1 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.450ns _inst_0/SLICE_549.Q0 to /tcnt_0/SLICE_487.C0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.450ns _inst_0/SLICE_549.Q0 to g_int_u/SLICE_548.A0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.103ns _inst_0/SLICE_549.Q0 to _inst_0/SLICE_549.B0 top_reveal_coretop_instance/top_la0_inst_0/even_parity
  e 0.450ns /tcnt_0/SLICE_272.Q0 to _inst_0/SLICE_460.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]
  e 0.103ns /tcnt_0/SLICE_372.F1 to /tcnt_0/SLICE_372.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/N_31
  e 0.450ns /tcnt_0/SLICE_372.F0 to /trig_u/SLICE_366.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[0]
  e 0.450ns /tcnt_0/SLICE_487.F0 to /trig_u/SLICE_364.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[2]
  e 0.450ns /tcnt_0/SLICE_489.F0 to /trig_u/SLICE_363.A1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/rd_dout_tcnt[1]
  e 0.450ns /trig_u/SLICE_366.F1 to _inst_0/SLICE_374.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/N_7
  e 0.103ns _inst_0/SLICE_374.F0 to _inst_0/SLICE_374.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 0.450ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_402.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 0.450ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_404.C1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 0.450ns _inst_0/SLICE_374.F0 to g_int_u/SLICE_410.C0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[0]
  e 0.450ns /trig_u/SLICE_364.F1 to g_int_u/SLICE_380.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[2]
  e 0.450ns /trig_u/SLICE_363.F1 to g_int_u/SLICE_394.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[1]
  e 0.450ns _inst_0/SLICE_460.F1 to g_int_u/SLICE_381.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_trig[3]
  e 0.450ns g_int_u/SLICE_548.F0 to c_RNO_2/SLICE_328.M0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_o3_0_1
  e 0.450ns RNO_2/SLICE_328.OFX0 to g_int_u/SLICE_123.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_2
  e 0.450ns g_int_u/SLICE_404.F1 to c_RNO_2/SLICE_328.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_6
  e 0.450ns _inst_0/SLICE_374.F1 to c_RNO_2/SLICE_328.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_25
  e 0.001ns g_int_u/SLICE_162.F0 to _int_u/SLICE_162.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_7[0]
  e 0.001ns g_int_u/SLICE_315.F0 to _int_u/SLICE_315.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1113_i
  e 0.001ns g_int_u/SLICE_315.F1 to _int_u/SLICE_315.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1112_i
  e 0.001ns g_int_u/SLICE_316.F0 to _int_u/SLICE_316.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1111_i
  e 0.001ns g_int_u/SLICE_316.F1 to _int_u/SLICE_316.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1139_i
  e 0.001ns g_int_u/SLICE_317.F0 to _int_u/SLICE_317.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1138_i
  e 0.001ns g_int_u/SLICE_317.F1 to _int_u/SLICE_317.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1137_i
  e 0.001ns int_u/SLICE_318.OFX0 to _int_u/SLICE_318.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_14[6]
  e 0.001ns g_int_u/SLICE_319.F0 to _int_u/SLICE_319.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1136_i
  e 0.001ns g_int_u/SLICE_320.F0 to _int_u/SLICE_320.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_12_i
  e 0.001ns g_int_u/SLICE_320.F1 to _int_u/SLICE_320.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1110_i
  e 0.001ns int_u/SLICE_321.OFX0 to _int_u/SLICE_321.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_57
  e 0.001ns g_int_u/SLICE_322.F0 to _int_u/SLICE_322.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1109_i
  e 0.001ns g_int_u/SLICE_322.F1 to _int_u/SLICE_322.DI1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_1108_i
  e 0.001ns g_int_u/SLICE_184.F0 to _int_u/SLICE_184.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_3
  e 0.001ns g_int_u/SLICE_123.F0 to _int_u/SLICE_123.DI0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_5
  e 0.450ns g_int_u/SLICE_122.Q0 to g_int_u/SLICE_112.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]
  e 0.450ns g_int_u/SLICE_122.Q1 to g_int_u/SLICE_112.D1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]
  e 0.103ns g_int_u/SLICE_112.F1 to g_int_u/SLICE_112.CE top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i
  e 0.450ns g_int_u/SLICE_379.F0 to g_int_u/SLICE_315.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[0]
  e 0.450ns g_int_u/SLICE_380.F0 to g_int_u/SLICE_315.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[1]
  e 0.450ns g_int_u/SLICE_381.F0 to g_int_u/SLICE_316.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[2]
  e 0.450ns g_int_u/SLICE_384.F0 to g_int_u/SLICE_316.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[3]
  e 0.450ns g_int_u/SLICE_385.F0 to g_int_u/SLICE_317.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[4]
  e 0.450ns g_int_u/SLICE_386.F0 to g_int_u/SLICE_317.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[5]
  e 0.450ns g_int_u/SLICE_387.F0 to g_int_u/SLICE_319.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[7]
  e 0.450ns g_int_u/SLICE_388.F0 to g_int_u/SLICE_320.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[9]
  e 0.450ns g_int_u/SLICE_389.F0 to g_int_u/SLICE_320.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[10]
  e 0.450ns g_int_u/SLICE_390.F0 to g_int_u/SLICE_322.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[12]
  e 0.450ns g_int_u/SLICE_391.F0 to g_int_u/SLICE_322.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11[14]
  e 0.450ns g_int_u/SLICE_536.F0 to g_int_u/SLICE_318.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
  e 0.450ns g_int_u/SLICE_537.F0 to g_int_u/SLICE_321.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
  e 0.450ns g_int_u/SLICE_394.F0 to g_int_u/SLICE_379.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[0]
  e 0.103ns g_int_u/SLICE_380.F1 to g_int_u/SLICE_380.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[1]
  e 0.103ns g_int_u/SLICE_381.F1 to g_int_u/SLICE_381.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
  e 0.103ns g_int_u/SLICE_384.F1 to g_int_u/SLICE_384.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m1[3]
  e 0.103ns g_int_u/SLICE_385.F1 to g_int_u/SLICE_385.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
  e 0.103ns g_int_u/SLICE_386.F1 to g_int_u/SLICE_386.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
  e 0.103ns g_int_u/SLICE_387.F1 to g_int_u/SLICE_387.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
  e 0.103ns g_int_u/SLICE_388.F1 to g_int_u/SLICE_388.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
  e 0.103ns g_int_u/SLICE_389.F1 to g_int_u/SLICE_389.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
  e 0.103ns g_int_u/SLICE_390.F1 to g_int_u/SLICE_390.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
  e 0.103ns g_int_u/SLICE_391.F1 to g_int_u/SLICE_391.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
  e 0.450ns g_int_u/SLICE_461.F1 to g_int_u/SLICE_394.C0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
  e 0.450ns g_int_u/SLICE_461.F0 to g_int_u/SLICE_380.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
  e 0.450ns _inst_0/SLICE_460.F0 to g_int_u/SLICE_381.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
  e 0.450ns _0/tm_u/SLICE_187.Q0 to g_int_u/SLICE_384.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[4]
  e 0.450ns _0/tm_u/SLICE_185.Q1 to g_int_u/SLICE_461.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[1]
  e 0.450ns _0/tm_u/SLICE_186.Q0 to g_int_u/SLICE_461.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[2]
  e 0.450ns _0/tm_u/SLICE_186.Q1 to _inst_0/SLICE_460.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[3]
  e 0.450ns _0/tm_u/SLICE_187.Q1 to g_int_u/SLICE_385.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
  e 0.450ns _0/tm_u/SLICE_187.Q1 to g_int_u/SLICE_387.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[5]
  e 0.450ns _0/tm_u/SLICE_188.Q0 to g_int_u/SLICE_386.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[6]
  e 0.450ns _0/tm_u/SLICE_188.Q1 to g_int_u/SLICE_536.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[7]
  e 0.450ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_388.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 0.450ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_390.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 0.450ns _0/tm_u/SLICE_189.Q0 to g_int_u/SLICE_391.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[10]
  e 0.450ns _0/tm_u/SLICE_189.Q1 to g_int_u/SLICE_389.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
  e 0.450ns _0/tm_u/SLICE_189.Q1 to g_int_u/SLICE_537.A0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[11]
  e 0.450ns g_int_u/SLICE_405.F0 to g_int_u/SLICE_376.C1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/rd_dout_tm_m_1[0]
  e 0.450ns g_int_u/SLICE_376.F1 to g_int_u/SLICE_402.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_RNIB0EF3
  e 0.450ns g_int_u/SLICE_402.F1 to g_int_u/SLICE_162.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g2_0
  e 0.450ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_349.B1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 0.450ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_405.C0 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 0.450ns _0/tm_u/SLICE_185.Q0 to g_int_u/SLICE_456.A1 top_reveal_coretop_instance/top_la0_inst_0/rd_dout_tm[0]
  e 0.450ns g_int_u/SLICE_407.F1 to g_int_u/SLICE_406.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
  e 0.450ns g_int_u/SLICE_407.F1 to g_int_u/SLICE_414.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/even_parity_RNIP6AL1
  e 0.450ns g_int_u/SLICE_456.F1 to g_int_u/SLICE_403.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/N_115_0
  e 0.450ns _inst_0/SLICE_549.F0 to g_int_u/SLICE_410.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_o4_1_0
  e 0.450ns g_int_u/SLICE_410.F0 to g_int_u/SLICE_123.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_o4_1_2
  e 0.450ns g_int_u/SLICE_349.F0 to g_int_u/SLICE_404.A1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_33
  e 0.450ns g_int_u/SLICE_403.F1 to g_int_u/SLICE_409.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1_1
  e 0.450ns g_int_u/SLICE_409.F1 to g_int_u/SLICE_123.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/m64_i_a3_0_1
  e 0.450ns g_int_u/SLICE_411.F1 to g_int_u/SLICE_123.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_0
  e 0.103ns g_int_u/SLICE_123.F1 to g_int_u/SLICE_123.B0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_1
  e 0.450ns g_int_u/SLICE_406.F1 to g_int_u/SLICE_123.D0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/g0_i_a4_0
  e 0.103ns g_int_u/SLICE_349.F1 to g_int_u/SLICE_349.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_36
  e 0.450ns g_int_u/SLICE_414.F0 to g_int_u/SLICE_411.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc_RNO_5

--------------------------------------------------------------------------------


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 5179 paths, 1 nets, and 3601 connections (95.62% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------